Forty years of feature-size predictions (1962-2002)

Author(s):  
C. Svensson
Keyword(s):  
Author(s):  
Peter Egger ◽  
Stefan Müller ◽  
Martin Stiftinger

Abstract With shrinking feature size of integrated circuits traditional FA techniques like SEM inspection of top down delayered devices or cross sectioning often cannot determine the physical root cause. Inside SRAM blocks the aggressive design rules of transistor parameters can cause a local mismatch and therefore a soft fail of a single SRAM cell. This paper will present a new approach to identify a physical root cause with the help of nano probing and TCAD simulation to allow the wafer fab to implement countermeasures.


2021 ◽  
Vol 27 (54) ◽  
pp. 13480-13480
Author(s):  
Maxime Tricoire ◽  
Luca Münzfeld ◽  
Jules Moutet ◽  
Nolwenn Mahieu ◽  
Léo La Droitte ◽  
...  
Keyword(s):  

Metals ◽  
2017 ◽  
Vol 7 (7) ◽  
pp. 275 ◽  
Author(s):  
Huixia Liu ◽  
Wenhao Zhang ◽  
Jenn-Terng Gau ◽  
Zongbao Shen ◽  
Youjuan Ma ◽  
...  

2012 ◽  
Vol 195 ◽  
pp. 128-131 ◽  
Author(s):  
Hun Hee Lee ◽  
Min Sang Yun ◽  
Hyun Wook Lee ◽  
Jin Goo Park

As the feature size of semiconductor device shrinks continuously, various high-K metals for 3-D structures have been applied to improve the device performance, such as high speed and low power consumption. Metal gate fabrication requires the removal of metal and polymer residues after etching process without causing any undesired etching and corrosion of metals. The conventional sulfuric-peroxide mixture (SPM) has many disadvantages like the corrosion of metals, environmental issues etc., DSP+(dilute sulfuric-peroxide-HF mixture) chemical is currently used for the removal of post etch residues on device surface, to replace the conventional SPM cleaning [. Due to the increased usage of metal gate in devices in recent times, the application of DSP+chemicals for cleaning processes also increases [.


2003 ◽  
Author(s):  
Chandana Yellampalli ◽  
Kunchinadka N. Bhat ◽  
Nandita DasGupta ◽  
Amitava DasGupta ◽  
Parimi R. Rao
Keyword(s):  

1998 ◽  
Vol 523 ◽  
Author(s):  
John Mardinly ◽  
David W. Susnitzky

AbstractThe demand for increasingly higher performance semiconductor products has stimulated the semiconductor industry to respond by producing devices with increasingly complex circuitry, more transistors in less space, more layers of metal, dielectric and interconnects, more interfaces, and a manufacturing process with nearly 1,000 steps. As all device features are shrunk in the quest for higher performance, the role of Transmission Electron Microscopy as a characterization tool takes on a continually increasing importance over older, lower-resolution characterization tools, such as SEM. The Ångstrom scale imaging resolution and nanometer scale chemical analysis and diffraction resolution provided by modem TEM's are particularly well suited for solving materials problems encountered during research, development, production engineering, reliability testing, and failure analysis. A critical enabling technology for the application of TEM to semiconductor based products as the feature size shrinks below a quarter micron is advances in specimen preparation. The traditional 1,000Å thick specimen will be unsatisfactory in a growing number of applications. It can be shown using a simple geometrical model, that the thickness of TEM specimens must shrink as the square root of the feature size reduction. Moreover, the center-targeting of these specimens must improve so that the centertargeting error shrinks linearly with the feature size reduction. To meet these challenges, control of the specimen preparation process will require a new generation of polishing and ion milling tools that make use of high resolution imaging to control the ion milling process. In addition, as the TEM specimen thickness shrinks, the thickness of surface amorphization produced must also be reduced. Gallium focused ion beam systems can produce hundreds of Ångstroms of amorphised surface silicon, an amount which can consume an entire thin specimen. This limitation to FIB milling requires a method of removal of amorphised material that leaves no artifact in the remaining material.


Author(s):  
Joshua Grose ◽  
Obehi G. Dibua ◽  
Dipankar Behera ◽  
Chee S. Foong ◽  
Michael Cullinan

Abstract Additive Manufacturing (AM) technologies are often restricted by the minimum feature size of parts they can repeatably build. The microscale selective laser sintering (μ-SLS) process, which is capable of producing single micron resolution parts, addresses this issue directly. However, the unwanted dissipation of heat within the powder bed of a μ-SLS device during laser sintering is a primary source of error that limits the minimum feature size of the producible parts. A particle scale thermal model is needed to characterize the thermal properties of the nanoparticles undergoing sintering and allow for the prediction of heat affected zones (HAZ) and the improvement of final part quality. Thus, this paper presents a method for the determination of the effective thermal conductivity of metal nanoparticle beds in a microscale selective laser sintering process using finite element simulations in ANSYS. CAD models of nanoparticle groups at various timesteps during sintering are developed from Phase Field Modeling (PFM) output data, and steady state thermal simulations are performed on each group. The complete simulation framework developed in this work is adaptable to particle groups of variable sizes and geometric arrangements. Results from the thermal models are used to estimate the thermal conductivity of the copper nanoparticles as a function of sintering duration.


2008 ◽  
Vol 2008 ◽  
pp. 1-4 ◽  
Author(s):  
Shuhong Li ◽  
Lifang Shi ◽  
Xiaochun Dong ◽  
Chunlei Du ◽  
Yudong Zhang

A convenient lithographic technique is proposed in this paper, which can be used to produce subdiffraction-limit arrays of nanopatterns over large areas (about several square centimeters). An array of polystyrene spheres (PS) is arranged on the surface of a layer of silver which has a thickness of about tens of nanometers. With the normal illumination light of wavelength 365 nm perpendicular to the substrate, PS can generate an array of optical patterns with high intensity at their contact points with silver. By designing the silver slab, the evanescent waves that carry subwavelength information about the optical patterns are substantially enhanced, while propagating components are restrained. In the photoresist which is on the other side of silver, the optical intensity is redistributed and subdiffraction-limit patterns are obtained after exposure and development. Simulation by finite-difference time-domain (FDTD) and experiments were carried out to verify the technique. The results show that by using PS with diameter of 600 nm, nanopatterns with dimension of less than 80 nm can be obtained.


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