Adaptive supply voltage and duty cycle controller for yield-power optimization of ICs

2017 ◽  
Author(s):  
Soonyoung Cha ◽  
Linda Milor
Keyword(s):  
Duty Cycle ◽  
Power Optimization ◽  
Supply Voltage

scholarly journals A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 860
Author(s):  
Shao-Ku Kao
Keyword(s):  
Duty Cycle ◽  
Delay Line ◽  
Supply Voltage ◽  
Cmos Process ◽  
Delay Lines ◽  
Clock Frequency ◽  
Quantization Method ◽  
Total Delay ◽  
Chip Area ◽  
Measurement Results

This paper proposes an all-digital duty cycle corrector with synchronous fast locking, and adopts a new quantization method to effectively produce a phase of 180 degrees or half delay of the input clock. By taking two adjacent rising edges input to two delay lines, the total delay time of the delay line is twice the other delay line. This circuit uses a 0.18 μm CMOS process, and the overall chip area is 0.0613 mm2, while the input clock frequency is 500 MHz to 1000 MHz, and the acceptable input clock duty cycle range is 20% to 80%. Measurement results show that the output clock duty cycle is 50% ± 2.5% at a supply voltage of 1.8 V operating at 1000 MHz, the power consumed is 10.1 mW, with peak-to-peak jitter of 9.89 ps.

A wideband receiver front-end with low noise and high linearity by exploiting reconfigurable dual paths in 180 nm CMOS

2021 ◽  
pp. 2150210
Author(s):  
Benqing Guo ◽  
Hongpeng Chen ◽  
Xuebing Wang ◽  
Lei Li ◽  
Wanting Zhou
Keyword(s):  
Duty Cycle ◽  
Noise Figure ◽  
Supply Voltage ◽  
Excitation Frequency ◽  
Low Noise ◽  
Resonance Structure ◽  
Front End ◽  
Main Path ◽  
Transconductance Amplifier ◽  
Simulation Results

In this paper, a wideband receiver front-end including the flexible reconfigurable main and auxiliary paths is proposed. Therein, the main path has the low-noise advantage thanks to the low-noise transconductance amplifier (LNTA) preceding the mixer and baseband. Meanwhile, by utilizing a mixer-first structure, the auxiliary path renders a high in-band and out-of-band linearity. Furthermore, an inductor resonance structure is also designed to mitigate the baseband noise crosstalk issue which is disclosed by a charging/discharging mechanism via the tail capacitance of passive mixers. Both of the receiving paths have shared a common baseband circuit while loading a commonly-shared 25% duty-cycle LO source generator. Simulation results by a 180 nm CMOS have demonstrated that the main path provides a low noise figure (NF) of 2.7 dB, while the auxiliary path obtains the in-band and out-of-band IIP3 of 9.2 and 21 dBm under typical LO excitation frequency of [Formula: see text] GHz. The power consumption of the main path of the dual-path front-end is 57 mW and that of the auxiliary path is 26 mW under a supply voltage of 1.8 V.

scholarly journals Exploration of dual supply voltage logic synthesis in state-of-the-art ASIC design flows

2003 ◽  
Vol 1 ◽  
pp. 185-189
Author(s):  
T. Mahnke ◽  
W. Stechele ◽  
M. Embacher ◽  
W. Hoeld
Keyword(s):  
Power Optimization ◽  
Supply Voltage ◽  
State Of The Art ◽  
Logic Synthesis ◽  
Design Environment ◽  
New Approach ◽  
Cell Library ◽  
Asic Design ◽  
Synthesis Methodology ◽  
Basic Evaluation

Abstract. Dual supply voltage scaling (DSVS) for logiclevel power optimization at the has increasingly attracted attention over the last few years. However, mainly due to the fact that the most widely used design tools do not support this new technique, it has still not become an integral part of real-world design flows. In this paper, a novel logic synthesis methodology that enables DSVS while relying entirely on standard tools is presented. The key to this methodology is a suitably modeled dual supply voltage (DSV) standard cell library. A basic evaluation of the methodology has been carried out on a number of MCNC benchmark circuits. In all these experiments, the results of state-of-the-art powerdriven single supply voltage (SSV) logic synthesis have been used as references in order to determine the true additional benefit of DSVS. Compared with the results of SSV power optimization, additional power reductions of 10% on average have been achieved. The results prove the feasibility of the new approach and reveal its greater efficiency in comparison with a well-known dedicated DSVS algorithm. Finally, the methodology has been applied to an embedded microcontroller core in order to further explore the potentials and limitations of DSVS in an existing industrial design environment.

scholarly journals A 3.0 Gsymbol/s/lane MIPI C-PHY Receiver with Adaptive Level-Dependent Equalizer for Mobile CMOS Image Sensor

Sensors ◽  
2021 ◽  
Vol 21 (15) ◽  
pp. 5197
Author(s):  
Seokwon Choi ◽  
Changmin Song ◽  
Young-Chan Jang
Keyword(s):  
Duty Cycle ◽  
High Speed ◽  
Supply Voltage ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Cmos Process ◽  
Peak Time ◽  
Time Jitter ◽  
Mobile Industry ◽  
Sensor Interfaces

A 3.0 Gsymbol/s/lane receiver is proposed herein to acquire near-grounded high-speed signals for the mobile industry processor interface (MIPI) C-PHY version 1.1 specification used for CMOS image sensor interfaces. Adaptive level-dependent equalization is also proposed to improve the signal integrity of the high-speed receivers receiving three-level signals. The proposed adaptive level-dependent equalizer (ALDE) is optimized by adjusting the duty cycle ratio of the clock recovered from the received data to 50%. A pre-determined data pattern transmitted from a MIPI C-PHY transmitter is established to perform the adaptive level-dependent equalization. The proposed MIPI C-PHY receiver with three data lanes is implemented using a 65 nm CMOS process with a 1.2 V supply voltage. The power consumption and area of each lane are 4.9 mW/Gsymbol/s/lane and 0.097 mm2, respectively. The proposed ALDE improves the peak-to-peak time jitter of 12 ps and 34 ps, respectively, for the received data and the recovered clock at a symbol rate of 3 Gsymbol/s/lane. Additionally, the duty cycle ratio of the recovered clock is improved from 42.8% to 48.3%.

First Demonstration of 2.1 kW Output Power at 425 MHz Using 4H-SiC RF Power BJTs

2006 ◽  
Vol 527-529 ◽  
pp. 1413-1416
Author(s):  
Anant K. Agarwal ◽  
Fatima Husna ◽  
Jeremy Haley ◽  
Howard Bartlow ◽  
Bill McCalpin ◽  
...  
Keyword(s):  
Output Power ◽  
Duty Cycle ◽  
Pulse Width ◽  
Supply Voltage ◽  
Input Pulse ◽  
Current Gain ◽  
Power Added Efficiency ◽  
Peak Output Power ◽  
Collector Efficiency ◽  
Dc Current

For the first time, 4H-SiC RF bipolar junction transistors have been used to produce an output power in excess of 2.1 kW at 425 MHz. For an input pulse width of 2 μs and 1% duty cycle, the power gain at peak output power is 6.3 dB with the collector efficiency and power added efficiency [PAE] being 45% and 35%, respectively, at a collector supply voltage of 75 V in a class C configuration. The package consists of 24 cells (2 chips) having an emitter periphery of approximately 1 inch per cell. Each cell produced a DC current gain (β) of 15 and a common emitter breakdown voltage (BVCEO) greater than 250 V. A peak output power of 87 W per cell was obtained at 425 MHz, as compared to the earlier report of 50 W per cell [1, 2] by using a shorter pulse width and duty cycle.

Wide-range CMOS reference clock generator with a dynamic duty cycle scaling mechanism at a 0.9-V supply voltage

2016 ◽  
Vol 24 (1) ◽  
pp. 71-78
Author(s):  
Wei-Bin Yang ◽  
Yu-Lung Lo ◽  
Kuo-Ning Chang ◽  
Yu-Yao Lin
Keyword(s):  
Duty Cycle ◽  
Supply Voltage ◽  
Clock Generator ◽  
Wide Range ◽  
Reference Clock

scholarly journals Efek Duty Cycle Pwm pada Pengendalian Kecepatan Motor BLDC 3 Phasa

2018 ◽  
Vol 1 (1) ◽  
pp. 14
Author(s):  
Rozlinda Dewi
Keyword(s):  
Duty Cycle ◽  
High Speed ◽  
Pulse Width Modulation ◽  
High Efficiency ◽  
Supply Voltage ◽  
Coefficient Of Determination ◽  
Motor Speed ◽  
Power Supply Voltage ◽  
Speed Change ◽  
Almost All

Nowadays almost all electric convertible equipments are in motion using Brushless Direct Current (BLDC) motors, because BLDC motors have high efficiency and energy density because the lack of brush makes BLDC motors reliable enough, maintenance is cheap and can be used for high speed. This research is more emphasized on the controller unit using DRV 11873 IC which has EVM (Evaluation Module) as strong magnetic induction enhancer in BLDC motor winding (stator) with Pulse Width Modulation (PWM) duty cycle mode, the result of research shows the relationship between the addition of duty cycle PWM and the addition of a large supply voltage V (V) given to the 3 phase Phas motor BLDC to the motor speed change (RPM). Through the calculation of coefficient of determination (R2) each experimental results between the change of power supply voltage (V) to the speed (RPM) obtained 0.998 and the calculation of coefficient of determination (R2) change duty cycle PWM signal to the speed (RPM) 0.996.

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