Novel Approach for the Reduction of Leakage Current Characteristics of 20 nm DRAM Capacitors With ZrO2–Based High-k Dielectrics

2017 ◽  
Vol 38 (11) ◽  
pp. 1524-1527
Author(s):  
Jong-Min Lee ◽  
Dong-Sik Park ◽  
Seung-chul Yew ◽  
Soo-Ho Shin ◽  
Jun-Yong Noh ◽  
...  
Author(s):  
Dong Gun Kim ◽  
Cheol Hyun An ◽  
Sanghyeon Kim ◽  
Dae Seon Kwon ◽  
Junil Lim ◽  
...  

Atomic layer deposited TiO2- and Al2O3-based high-k gate insulator (GI) were examined for the Ge-based metal-oxide-semiconductor capacitor application. The single-layer TiO2 film showed a too high leakage current to be...


2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.


2021 ◽  
pp. 106413
Author(s):  
Yuexin Yang ◽  
Zhuohui Xu ◽  
Tian Qiu ◽  
Honglong Ning ◽  
Jinyao Zhong ◽  
...  

2001 ◽  
Vol 685 ◽  
Author(s):  
Won-Jae Lee ◽  
Chang-Ho Shin ◽  
In-Kyu You ◽  
Il-Suk Yang ◽  
Sang-Ouk Ryu ◽  
...  

AbstractThe SrTa2O6 (STO) thin films were prepared by plasma enhanced atomic layer deposition (PEALD) with alternating supply of reactant sources, Sr[Ta(C2H5O)5(C4H10NO)]2 {Strontium bis-[tantalum penta-ethoxide dimethyllaminoethoxide]; Sr(Ta(OEt)5▪dmae)2} and O2plasma. It was observed that the uniform and conformal STO thin films were successfully deposited using PEALD and the film thickness per cycle was saturated at about 0.8 nm at 300°C. Electrical properties of SrTa2O6 (STO) thin films prepared on Pt/SiO2/Si substrates with annealing temperatures have been investigated. While the grain size and dielectric constant of STO films increased with increasing annealing temperature, the leakage current characteristics of STO films slightly deteriorated. The leakage current density of a 40nm-STO film was about 5×10−8A/cm2 at 3V.


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