Investigation of ultra-thin gate oxide reliability behavior by separate characterization of soft breakdown and hard breakdown

2002 ◽  
Author(s):  
T. Pompl ◽  
H. Wurzer ◽  
M. Kerber ◽  
I. Eisele
Keyword(s):  
Gate Oxide ◽  
Oxide Reliability ◽  
Thin Gate Oxide ◽  
Soft Breakdown

Modeling Soft Breakdown of Ultra-Thin Gate Oxide Layers

1999 ◽  
Vol 567 ◽  
Author(s):  
Michel Houssa ◽  
P.W. Mertens ◽  
M.M. Heyns
Keyword(s):  
Gate Voltage ◽  
Dielectric Breakdown ◽  
Percolation Cluster ◽  
Gate Oxide ◽  
Oxide Layers ◽  
Long Range Correlations ◽  
Electrical Stress ◽  
Non Gaussian ◽  
Thin Gate Oxide ◽  
Soft Breakdown

ABSTRACTThe time-dependent dielectric breakdown of MOS capacitors with ultra-thin gate oxide layers is investigated. After the occurrence of soft breakdown, the gate current increases by 3 to 4 orders of magnitudes and behaves like a power law of the applied gate voltage. It is shown that this behavior can be explained by assuming that a percolation path is formed between the electron traps generated in the gate oxide layer during electrical stress of the capacitors. The time dependence of the gate voltage signal after soft breakdown is next analysed. It is shown that the fluctuations in the gate voltage are non-gaussian as well as that long-range correlations exist in the system after soft breakdown. These results can be explained by a dynamic percolation model, taking into account the trapping-detrapping of charges within the percolation cluster formed at soft breakdown.

Reliability and Ruggedness of 1200V SiC Planar Gate MOSFETs Fabricated in a High Volume CMOS Foundry

2018 ◽  
Vol 924 ◽  
pp. 697-702 ◽  
Author(s):  
Sauvik Chowdhury ◽  
Levi Gant ◽  
Blake Powell ◽  
Kasturirangan Rangaswamy ◽  
Kevin Matocha
Keyword(s):  
Room Temperature ◽  
Stress Testing ◽  
Short Circuit ◽  
Gate Oxide ◽  
High Volume ◽  
Inductive Load ◽  
Switching Losses ◽  
Oxide Reliability ◽  
Silicon Cmos

This paper presents the performance, reliability and ruggedness characterization of 1200V, 80mΩ rated SiC planar gate MOSFETs, fabricated in a high volume, 150mm silicon CMOS foundry. The devices showed a specific on-resistance of 5.1 mΩ.cm2 at room temperature, increasing to 7.5 mΩ.cm2 at 175 °C. Total switching losses were less than 300μJ (VDD = 800V, ID = 20A). The devices showed excellent gate oxide reliability with VTH shifts under 0.2V for extended HTGB stress testing at 175 °C for up to 5500 hours (VGS = 25V) and 2500 hours (VGS = -10V). Ruggedness performance such as unclamped inductive load switching and short circuit capability are also discussed.

TXRF Characterization of Trace Metal Contamination in Thin Gate Oxides

1992 ◽  
Vol 259 ◽  
Author(s):  
R. S. Hockett ◽  
Diane Hymes
Keyword(s):  
Metal Contamination ◽  
Gate Oxide ◽  
Silicon Substrates ◽  
Qualitative Information ◽  
Gate Oxides ◽  
Quantitative Estimates ◽  
Oxide Reliability ◽  
First Time ◽  
Non Destructive

ABSTRACTMetal contamination on the surface of silicon substrates before gate oxidation is known to affect gate oxide reliability. For the first time this study presents a non-destructive, analytical measurement of transition metals in an 8nm gate oxide grown by a 920 °C-10min-dry oxidation of an intentionally contaminated silicon surface. The TECHNOS TREX 610 TXRF anglescan of the gate oxide provides qualitative information on the location of the metals. The data indicate the Fe is on or in the oxide, the Cu is below the oxide, the Zn is on the oxide, and the Ni may be both in the oxide and below the oxide layer. In addition, quantitative estimates from the TXRF data indicate that all the original Fe and Cu are present, while only portions of Zn and Ni are detected after the oxidation.

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