Stress induced leakage current and bulk oxide trapping: temperature evolution

Author(s):  
G. Ghidini ◽  
A. Sebastiani ◽  
D. Brazzelli
2002 ◽  
Vol 716 ◽  
Author(s):  
Yi-Mu Lee ◽  
Yider Wu ◽  
Joon Goo Hong ◽  
Gerald Lucovsky

AbstractConstant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.


2015 ◽  
Vol 118 (16) ◽  
pp. 164101 ◽  
Author(s):  
Y. Li ◽  
A. Leśniewska ◽  
O. Varela Pedreira ◽  
J.-F. de Marneffe ◽  
I. Ciofi ◽  
...  

1999 ◽  
Vol 75 (5) ◽  
pp. 734-736 ◽  
Author(s):  
Nian-Kai Zous ◽  
Tahui Wang ◽  
Chih-Chich Yeh ◽  
C. W. Tsai ◽  
Chimoon Huang

2019 ◽  
Vol 6 (7) ◽  
pp. 076401
Author(s):  
V A Gritsenko ◽  
A A Gismatulin ◽  
A P Baraban ◽  
A Сhin

2001 ◽  
Vol 41 (9-10) ◽  
pp. 1421-1425 ◽  
Author(s):  
F. Lime ◽  
G. Ghibauda ◽  
G. Guégan

2010 ◽  
Vol 1252 ◽  
Author(s):  
Sahar Sahhaf ◽  
Robin Degraeve ◽  
Mohammed Zahid ◽  
Guido Groeseneken

AbstractIn this work, the effect of elevated temperature on the generated defects with constant voltage stress (CVS) in SiO2 and SiO2/HfSiO stacks is investigated. Applying Trap Spectroscopy by Charge Injection and Sensing (TSCIS) to 6.5 nm SiO2 layers, different kinds of generated traps are profiled at low and high temperature. Also the Stress-Induced Leakage Current (SILC) spectrum of high-k dielectric stack is different at elevated temperature indicating that degradation and breakdown at high temperature is not equivalent to that at low temperature and therefore, extrapolation of data from high to low T or vice versa is challenging.


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