Correlation of stress-induced leakage current with generated positive trapped charges for ultrathin gate oxide

ABSTRACTCorona charging in air combined with non-contact oxide charge measurement with a contact potential difference probe provides an unique possibility for fast monitoring of electron tunneling characteristics without preparation of MOS capacitors. It has also been found tha corona charging of thin oxides in the tunneling range is very effective in generating stressinduced leakage current. In this work we demonstrate the sensitivity of the corona stressinduced leakage current magnitude to gate oxide integrity defect density. The experimenta results cover three of the most common gate oxide integrity defects, namely: 1 – the defect induced by heavy metals (Fe.Cu) at a practically important low concentration range of 1×1010 to 1×1011 atoms/cm3: 2 – the defects originating from interface roughness and 3–the defects related to crystal originated particles.At low corona stress fluence, these defects play no role in the tunneling characteristics which follow ideal Fowler-Nordheim characteristics for oxides 50Å or thicker and a contribution from a direct tunneling current for thinner oxides. At high corona stress fluences, gate oxide integrity defects control the magnitude of stress-induced leakage current measured at constan oxide field. It is suggested that the gate oxide integrity role is associated with the enhanced rate of the trap generation during stress. It is noted that the present findings employ a novel methodology for gate oxide integrity monitoring based on corona charging and contact potential difference measurement.

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The gate oxide lifetime limited by `B-mode' stress induced leakage current and the scaling limit of silicon dioxides in the direct tunnelling regime

Semiconductor Science and Technology ◽

10.1088/0268-1242/15/5/307 ◽

2000 ◽

Vol 15 (5) ◽

pp. 478-484 ◽

Cited By ~ 25

Author(s):

Kenji Okada

Keyword(s):

Leakage Current ◽

Scaling Limit ◽

Gate Oxide ◽

Mode Stress ◽

Stress Induced Leakage Current

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Degradation and SILC Effects of RPECVD sub-2.0nm Oxide/Nitride and Oxynitride Dielectrics Under Constant Current Stress

MRS Proceedings ◽

10.1557/proc-716-b2.9 ◽

2002 ◽

Vol 716 ◽

Cited By ~ 1

Author(s):

Yi-Mu Lee ◽

Yider Wu ◽

Joon Goo Hong ◽

Gerald Lucovsky

Keyword(s):

Leakage Current ◽

Electrical Performance ◽

Constant Current ◽

Continuous Increase ◽

Current Stress ◽

Thermal Oxide ◽

Stress Induced Leakage Current ◽

Boron Penetration ◽

Soft Breakdown ◽

Induced Defects

AbstractConstant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.

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Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

MRS Proceedings ◽

10.1557/opl.2013.585 ◽

2013 ◽

Vol 1538 ◽

pp. 291-302

Author(s):

Edward Yi Chang ◽

Hai-Dang Trinh ◽

Yueh-Chin Lin ◽

Hiroshi Iwai ◽

Yen-Ku Lin

Keyword(s):

Low Power ◽

Leakage Current ◽

High Speed ◽

High Performance ◽

Gate Oxide ◽

Chemical Cleaning ◽

Low Leakage ◽

Low Leakage Current ◽

High K ◽

Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

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