Stability Analysis of Parasitic Coupling Between on-Chip Antenna and mm-Wave Front-End

Author(s):  
Simon Ooms ◽  
Patrick Reynaert
IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 43190-43204 ◽  
Author(s):  
Mahsa Keshavarz Hedayati ◽  
Abdolali Abdipour ◽  
Reza Sarraf Shirazi ◽  
Max J. Ammann ◽  
Matthias John ◽  
...  

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1264
Author(s):  
Mohammad Alibakhshikenari ◽  
Bal S. Virdee ◽  
Ayman A. Althuwayb ◽  
Dion Mariyanayagam ◽  
Ernesto Limiti

The results presented in this paper show that by employing a combination of metasurface and substrate integrated waveguide (SIW) technologies, we can realize a compact and low-profile antenna that overcomes the drawbacks of narrow-bandwidth and low-radiation properties encountered by terahertz antennas on-chip (AoC). In addition, an effective RF cross-shaped feed structure is used to excite the antenna from its underside by coupling, electromagnetically, RF energy through the multi-layered antenna structure. The feed mechanism facilitates integration with the integrated circuits. The proposed antenna is constructed from five stacked layers, comprising metal–silicon–metal–silicon–metal. The dimensions of the AoC are 1 × 1 × 0.265 mm3. The AoC is shown to have an impedance match, radiation gain and efficiency of ≤ −15 dB, 8.5 dBi and 67.5%, respectively, over a frequency range of 0.20–0.22 THz. The results show that the proposed AoC design is viable for terahertz front-end applications.


Author(s):  
Fabio Aquilino ◽  
Francesco G. Della Corte ◽  
Letizia Fragomeni ◽  
Massimo Merenda ◽  
Fabio Zito

2021 ◽  
Vol 11 (2) ◽  
pp. 22
Author(s):  
Umberto Ferlito ◽  
Alfio Dario Grasso ◽  
Michele Vaiana ◽  
Giuseppe Bruno

Charge-Based Capacitance Measurement (CBCM) technique is a simple but effective technique for measuring capacitance values down to the attofarad level. However, when adopted for fully on-chip implementation, this technique suffers output offset caused by mismatches and process variations. This paper introduces a novel method that compensates the offset of a fully integrated differential CBCM electronic front-end. After a detailed theoretical analysis of the differential CBCM topology, we present and discuss a modified architecture that compensates mismatches and increases robustness against mismatches and process variations. The proposed circuit has been simulated using a standard 130-nm technology and shows a sensitivity of 1.3 mV/aF and a 20× reduction of the standard deviation of the differential output voltage as compared to the traditional solution.


2019 ◽  
Vol 18 (11) ◽  
pp. 2404-2408 ◽  
Author(s):  
Janusz Grzyb ◽  
Marcel Andree ◽  
Ritesh Jain ◽  
Bernd Heinemann ◽  
Ullrich R. Pfeiffer

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