TCAD analysis of FinFET stress engineering for CMOS technology scaling

Author(s):  
Amaury Gendron-Hansen ◽  
Konstantin Korablev ◽  
Ivan Chakarov ◽  
James Egley ◽  
Jin Cho ◽  
...  
MRS Advances ◽  
2017 ◽  
Vol 2 (52) ◽  
pp. 2973-2982 ◽  
Author(s):  
Andreas Kerber

ABSTRACTMG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.


2016 ◽  
Vol 833 ◽  
pp. 135-139
Author(s):  
Dayang Nur Salmi Dharmiza Awang Salleh ◽  
Rohana Sapawi

Recent technology requires multistandard Radio Frequency (RF) chips for multipurpose wireless applications. In RF circuits, a low-noise amplifier (LNA) plays the key role in determining the receiver’s performance. With CMOS technology scaling, various designs has been adopted to study circuit’s characteristic and variation. In this paper, we present the results of scalable wideband LNA design based on complementary metal oxide semiconductor (CMOS), with its variance study. The design was fabricated in 180nm, 90nm, 65nm and 40nm CMOS technology.


1999 ◽  
Vol 592 ◽  
Author(s):  
G. Groeseneken ◽  
R. Degraeve ◽  
B. Kaczer ◽  
H.E. Maes

ABSTRACTThis paper discusses the evolution in the degradation and breakdown behaviour of ultra-thin oxides when scaling the oxide thickness into the sub-4 nm range for future CMOS technology generations. It will be shown that changes in the breakdown statistics, which can be explained by a percolation model for breakdown, lead to an increased area dependence of the time-tobreakdown. This has to be taken into account when predicting the oxide reliability. Also the impact of the test methodology, the relevance of a so-called polarity gap in the charge-tobreakdown and its consequences for reliability testing, are highlighted. Moreover, a strong increase in the temperature dependence of breakdown, especially for sub-3 nm oxides, is demonstrated and the impact of temperature on trap generation and critical trap density at breakdown is discussed. Finally it is shown that the combined effects of all these phenomena might lead to oxide reliability becoming a potential showstopper for further technology scaling.


Author(s):  
C.-H. Jan ◽  
M. Agostinelli ◽  
H. Deshpande ◽  
M. A. El-Tanani ◽  
W. Hafez ◽  
...  

2015 ◽  
Vol 62 (12) ◽  
pp. 3945-3950 ◽  
Author(s):  
Peng Zheng ◽  
Daniel Connelly ◽  
Fei Ding ◽  
Tsu-Jae King Liu

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