Optoelectronic and Microwave Transmission Characteristics of Indium Solder Bumps for Low-Temperature Flip-Chip Applications

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

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Demonstration of fine pitch FCOB (Flip Chip on Board) assembly based on solder bumps at Fermilab

Journal of Instrumentation ◽

10.1088/1748-0221/4/11/t11001 ◽

2009 ◽

Vol 4 (11) ◽

pp. T11001-T11001

Author(s):

E Skup ◽

M Trimpl ◽

R Yarema ◽

J C Yun

Keyword(s):

Flip Chip ◽

Fine Pitch ◽

Solder Bumps

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Isotropically conductive adhesives and solder bumps for flip chip on board circuits-a comparison of lifetime under thermal cycling

Proceedings of 3rd International Conference on Adhesive Joining and Coating Technology in Electronics Manufacturing 1998 (Cat. No.98EX180) ◽

10.1109/adhes.1998.742014 ◽

2002 ◽

Cited By ~ 4

Author(s):

J.B. Nysaether ◽

Z. Lai ◽

J. Liu

Keyword(s):

Thermal Cycling ◽

Flip Chip ◽

Conductive Adhesives ◽

Solder Bumps

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Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

Volume 5: Electronics and Photonics ◽

10.1115/imece2007-42571 ◽

2007 ◽

Author(s):

Jin Yang ◽

Charles Ume

Keyword(s):

Defect Detection ◽

Flip Chip ◽

Solder Bump ◽

Temporal Coherence ◽

Coherence Analysis ◽

Laser Ultrasound ◽

Surface Mount ◽

Flip Chips ◽

Solder Bumps ◽

Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

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Effect of High Temperature Storage on Reliability of Sn-Ag-Cu Flip Chip Solder Bumps

2006 International Conference on Electronic Materials and Packaging ◽

10.1109/emap.2006.4430604 ◽

2006 ◽

Author(s):

Xingjia Huang ◽

S.W. Ricky Lee ◽

Ming Li ◽

William T. Chen

Keyword(s):

High Temperature ◽

Flip Chip ◽

Solder Bumps ◽

High Temperature Storage ◽

Temperature Storage

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Fabrication and Packaging of CMUT Using Low Temperature Co-Fired Ceramic

Micromachines ◽

10.3390/mi9110553 ◽

2018 ◽

Vol 9 (11) ◽

pp. 553 ◽

Cited By ~ 7

Author(s):

Fikret Yildiz ◽

Tadao Matsunaga ◽

Yoichi Haga

Keyword(s):

Low Temperature ◽

Integrated Circuit ◽

Flip Chip ◽

Ultrasonic Transducer ◽

Silicon On Insulator ◽

Anodic Bonding ◽

Lateral Side ◽

Membrane Thickness ◽

Bonding Performance ◽

Complex Admittance

This paper presents fabrication and packaging of a capacitive micromachined ultrasonic transducer (CMUT) using anodically bondable low temperature co-fired ceramic (LTCC). Anodic bonding of LTCC with Au vias-silicon on insulator (SOI) has been used to fabricate CMUTs with different membrane radii, 24 µm, 25 µm, 36 µm, 40 µm and 60 µm. Bottom electrodes were directly patterned on remained vias after wet etching of LTCC vias. CMUT cavities and Au bumps were micromachined on the Si part of the SOI wafer. This high conductive Si was also used as top electrode. Electrical connections between the top and bottom of the CMUT were achieved by Au-Au bonding of wet etched LTCC vias and bumps during anodic bonding. Three key parameters, infrared images, complex admittance plots, and static membrane displacement, were used to evaluate bonding success. CMUTs with a membrane thickness of 2.6 µm were fabricated for experimental analyses. A novel CMUT-IC packaging process has been described following the fabrication process. This process enables indirect packaging of the CMUT and integrated circuit (IC) using a lateral side via of LTCC. Lateral side vias were obtained by micromachining of fabricated CMUTs and used to drive CMUTs elements. Connection electrodes are patterned on LTCC side via and a catheter was assembled at the backside of the CMUT. The IC was mounted on the bonding pad on the catheter by a flip-chip bonding process. Bonding performance was evaluated by measurement of bond resistance between pads on the IC and catheter. This study demonstrates that the LTCC and LTCC side vias scheme can be a potential approach for high density CMUT array fabrication and indirect integration of CMUT-IC for miniature size packaging, which eliminates problems related with direct integration.

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