On-Chip Two-Phase Cooling With Refrigerant 85 $\mu{\rm m}$-Wide Multi-Microchannel Evaporator Under Hot-Spot Conditions

Author(s):  
Etienne Costa-Patry ◽  
Stefano Nebuloni ◽  
Jonathan Olivier ◽  
John Richard Thome
Keyword(s):  
Hot Spot ◽  
On Chip ◽  
Author(s):  
Sung-Yong Park ◽  
Jiangtao Cheng ◽  
Chung-Lung (C.-L. ) Chen

Electrowetting-on-dielectric (EWOD) has attracted as one of the effective on-chip cooling technologies. It enables rapid transport of coolant droplets and heat transfer from target heat sources, while consuming extremely low power for fluid transport. However, a sandwiched configuration in conventional EWOD devices only allows sensible heat transfer, which very limits heat transfer capability of the device. In this paper, we report a novel single-sided EWOD (SEWOD) technology that enables two-phase cooling on a single-sided plate. As a result, heat transfer capability of the SEWOD device can be significantly enhanced. A complete set of droplet manipulation functions necessary for active hot spot cooling has been achieved on SEWOD. Hot spot surface modification to hydrophilic makes a droplet stick on a hot spot and maximize its contact area, greatly improving thermal rejection capability of the device. We have demonstrated two-phase cooling on SEWOD. With successive transportation of four droplets with a volume of 30 μL, the hot spot temperature that was initially heated up to 172°C was able to be stably maintained below 100 °C for 475s. This novel SEWOD-driven cooling technique promises to potentially function as a wickless vapor chamber with enhanced thermal managing capabilities.


2010 ◽  
Vol 132 (4) ◽  
Author(s):  
Yoon Jo Kim ◽  
Yogendra K. Joshi ◽  
Andrei G. Fedorov ◽  
Young-Joon Lee ◽  
Sung-Kyu Lim

It is now widely recognized that the three-dimensional (3D) system integration is a key enabling technology to achieve the performance needs of future microprocessor integrated circuits (ICs). To provide modular thermal management in 3D-stacked ICs, the interlayer microfluidic cooling scheme is adopted and analyzed in this study focusing on a single cooling layer performance. The effects of cooling mode (single-phase versus phase-change) and stack/layer geometry on thermal management performance are quantitatively analyzed, and implications on the through-silicon-via scaling and electrical interconnect congestion are discussed. Also, the thermal and hydraulic performance of several two-phase refrigerants is discussed in comparison with single-phase cooling. The results show that the large internal pressure and the pumping pressure drop are significant limiting factors, along with significant mass flow rate maldistribution due to the presence of hot-spots. Nevertheless, two-phase cooling using R123 and R245ca refrigerants yields superior performance to single-phase cooling for the hot-spot fluxes approaching ∼300 W/cm2. In general, a hybrid cooling scheme with a dedicated approach to the hot-spot thermal management should greatly improve the two-phase cooling system performance and reliability by enabling a cooling-load-matched thermal design and by suppressing the mass flow rate maldistribution within the cooling layer.


2012 ◽  
Vol 41 ◽  
pp. 36-51 ◽  
Author(s):  
Jackson Braz Marcinichen ◽  
Jonathan Albert Olivier ◽  
John Richard Thome

Author(s):  
Jackson B. Marcinichen ◽  
Brian P. d’Entremont ◽  
John R. Thome ◽  
Gary Bulman ◽  
Jay Lewis ◽  
...  

This study concerns cooling of electronic components of intense background heat flux with one ultra intense hot spot (e.g. 1000 Wcm−2 on a footprint of 1 cm × 1 cm with 5000 Wcm−2 applied to a 0.02 cm × 0.02 cm region at the center). To manage these extreme heat fluxes and consequently surpass the thermal-hydrodynamic challenges and design paradigms, for example as specified in a recent DARPA request for proposals (Intrachip/Interchip Enhanced Cooling Fundamentals - ICECool Fundamentals [1]), on-chip two-phase multi-microchannel cooling integrated with a superlattice (SL) thin-film thermoeletric cooling (TEC) technology was investigated via computer simulations. The simulations showed that increasing TEC electrical current results in greater enhancement of heat flow through the TEC, but at high currents this benefit is offset by a net addition of heat to the system, which must also be evacuated by the microchannels. When optimized, a minimum peak junction temperature of about 86 °C for a current of about 8 A was found, which represented a reduction of about 4 °C from a maximum allowed 90 °C at the ultra-intense hot-spot, thus potentially significantly capable of exceeding the DARPA [1] requirement, due to the embedded SL TEC within the microevaporator (ME) structure.


2012 ◽  
Vol 134 (5) ◽  
Author(s):  
Avram Bar-Cohen ◽  
Peng Wang

The rapid emergence of nanoelectronics, with the consequent rise in transistor density and switching speed, has led to a steep increase in microprocessor chip heat flux and growing concern over the emergence of on-chip hot spots. The application of on-chip high flux cooling techniques is today a primary driver for innovation in the electronics industry. In this paper, the physical phenomena underpinning the most promising on-chip thermal management approaches for hot spot remediation, along with basic modeling equations and typical results are described. Attention is devoted to thermoelectric micro-coolers and two-phase microgap coolers. The advantages and disadvantages of these on-chip cooling solutions for high heat flux hot spots are evaluated and compared.


2013 ◽  
Vol 455 ◽  
pp. 466-469
Author(s):  
Yun Chuan Wu ◽  
Shang Long Xu ◽  
Chao Wang

With the increase of performance demands, the nonuniformity of on-chip power dissipation becomes greater, causing localized high heat flux hot spots that can degrade the processor performance and reliability. In this paper, a three-dimensional model of the copper microchannel heat sink, with hot spot heating and background heating on the back, was developed and used for numerical simulation to predict the hot spot cooling performance. The hot spot is cooled by localized cross channels. The pressure drop, thermal resistance and effects of hot spot heat flux and fluid flow velocity on the cooling of on-chip hot spots, are investigated in detail.


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