scholarly journals Discrete-Pulsed Current Time Method to Estimate Channel Thermal Resistance of GaN-Based Power Devices

2018 ◽  
Vol 65 (12) ◽  
pp. 5301-5306 ◽  
Author(s):  
Zheng Xu ◽  
Saptarshi Mandal ◽  
Jianyi Gao ◽  
Harshad Surdi ◽  
Wenwen Li ◽  
...  
Energies ◽  
2020 ◽  
Vol 13 (3) ◽  
pp. 557
Author(s):  
Gabor Farkas ◽  
Dirk Schweitzer ◽  
Zoltan Sarkany ◽  
Marta Rencz

Traditionally the thermal behavior of power devices is characterized by temperature measurements at the junction and at accessible external points. In large modules composed of thin chips and materials of high thermal conductivity the shape and distribution of the heat trajectories are influenced by the external boundary represented by the cooling mount. This causes mediocre repeatability of the characteristic RthJC junction to case thermal resistance even in measurements at the same laboratory and causes very poor reproducibility among sites using dissimilar instrumentation. The Transient Dual Interface Methodology (TDIM) is based on the comparison of measured structure functions. With this method high repeatability can be achieved although introducing severe changes into the measurement environment is the essence of this test scheme. There is a systematic difference between thermal data measured with TDIM method and that measured with temperature probes, but we found that this difference was smaller than the scatter of the latter method. For checking production stability, we propose the use of a structure function-based Rth@Cth thermal metric, which is the thermal resistance value reached at the thermal capacitance belonging to the mass of the package base. This metric condenses the consistency of internal structural elements into a single number.


2013 ◽  
Vol 347-350 ◽  
pp. 1630-1634
Author(s):  
Xiao Ming Ding ◽  
Gang Chen ◽  
Dian Li Wang

Wherever possible, we have adopted the newest modern technology. The Au-Si binary alloy sintered chips are silicon or silicon carbide power devices. The sintered temperature is 380 to 390 °C. Using micro-infrared thermal image instrument, compares the microwave transient infrared thermal image test results of sample devices which chips welded process under two different process condition. Measured results show that the thermal resistance after chip welded process optimized is twenty percent smaller than before. It describes the importance of controlling the chip welded process parameters during assembly.


2000 ◽  
Author(s):  
Hyun-Min Park ◽  
Sang-Woong Yoon ◽  
Sang-Hoon Cheon ◽  
Songcheol Hong

2012 ◽  
Vol 101 (5) ◽  
pp. 052108 ◽  
Author(s):  
ZhiKun Zhang ◽  
Jiming Bian ◽  
Jingchang Sun ◽  
Zhenhe Ju ◽  
Yuxin Wang ◽  
...  

2008 ◽  
Vol 600-603 ◽  
pp. 1251-1256 ◽  
Author(s):  
Lin Lin Liu ◽  
Ting Gang Zhu ◽  
Michael Murphy ◽  
Marek Pabisz ◽  
Milan Pophristic ◽  
...  

The first commercially viable high voltage (>600V) gallium nitride (GaN) Schottky barrier devices are reported. Though GaN does not have any “micropipe” defects, which commonly exists in SiC material, defects like dislocations due to lattice mismatch hamper the material development of GaN high power devices. Improvements in the nitride epitaxial film growth have led to significant reduction of conductive dislocations. Conductive Atomic Force Microscope (CAFM) analysis of conductive dislocations shows only on the order of 103 cm-2 density of conductive dislocations, which are believed to be responsible for the undesired leakage current. GaN diodes compare to SiC or Si devices demonstrate a significant advantage in the thermal resistance. The insulating properties of Sapphire substrates allow fabrication of the devices in TO220 packages with insulating frame and thermal resistance better than 1.8°C/W compare to 3°C/W of SiC or Si devices with insulating frame. Performance of GaN, SiC and Si devices in the switch mode power supplies is compared.


Author(s):  
Koji Nishi

Abstract Power electronics is becoming more important than before with motor application expansion. For size reduction of inverter integrated motor design, accurate temperature prediction of power devices is becoming critical. For up to several hundred-watt motor system, inverter is designed with discrete power devices with standard package. This paper investigates package thermal resistance of a DPAK package as an example. Firstly, three-dimensional heat conduction simulation only with DPAK package model is conducted. It is found that its package thermal resistance changes by ∼6.2°C/W due to boundary condition variation. After that, simulation not only with DPAK package but also with PCB is conducted to understand package thermal resistance of a real system implementation case. It is found that package thermal resistance varies drastically by copper trace size. “Smallest” case with minimum copper traces shows ∼0.9 °C/W higher value than larger copper trace case and shows ∼1.5 °C/W higher value than the case that copper trace fully covers PCB top surface, in the case that horizontal PCB size is 50 × 50 mm. After that, two types of test boards with different trace size for of n-channel MOSFET with DPAK package are prepared. Measurements are conducted to know package thermal resistance variation by copper trace size. Transient thermal impedance curve is obtained from measurement result and is converted to a cumulative Rth-Cth curve to know and discuss the difference by copper trace size of these two test boards. The difference is also discussed with and compared to that of simulation results.


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