Investigation Regarding Thermal Resistance of Surface Mount Type Discrete Power Semiconductor Package

Author(s):  
Koji Nishi

Abstract Power electronics is becoming more important than before with motor application expansion. For size reduction of inverter integrated motor design, accurate temperature prediction of power devices is becoming critical. For up to several hundred-watt motor system, inverter is designed with discrete power devices with standard package. This paper investigates package thermal resistance of a DPAK package as an example. Firstly, three-dimensional heat conduction simulation only with DPAK package model is conducted. It is found that its package thermal resistance changes by ∼6.2°C/W due to boundary condition variation. After that, simulation not only with DPAK package but also with PCB is conducted to understand package thermal resistance of a real system implementation case. It is found that package thermal resistance varies drastically by copper trace size. “Smallest” case with minimum copper traces shows ∼0.9 °C/W higher value than larger copper trace case and shows ∼1.5 °C/W higher value than the case that copper trace fully covers PCB top surface, in the case that horizontal PCB size is 50 × 50 mm. After that, two types of test boards with different trace size for of n-channel MOSFET with DPAK package are prepared. Measurements are conducted to know package thermal resistance variation by copper trace size. Transient thermal impedance curve is obtained from measurement result and is converted to a cumulative Rth-Cth curve to know and discuss the difference by copper trace size of these two test boards. The difference is also discussed with and compared to that of simulation results.

2010 ◽  
Vol 148-149 ◽  
pp. 429-433
Author(s):  
Ming Chen ◽  
Yan Ting Yu ◽  
Bo Wang ◽  
Yong Tang

As the operation performances and reliability of semiconductor devices are tightly related to its operating temperature, the research on the heat transfer characteristic and thermal modeling do a significant meaning to extend services lifetime and improve application reliability of the IGBT modules. The physical structure and the conception, RC component network of thermal resistance, test principle and platform of the transient thermal impedance of IGBT module and three modeling methods are briefly introduced. The parameters of Cauer RC thermal network of a certain type IGBT is derived based on transmission line method. The junction-case thermal resistance can be deduced by Finite Element Method in the numerical simulator ANSYS and the transient thermal impedance curve. Thermal compact model can also be deduced from the numerical simulation and experimental results. An excellent agreement is obtained between experimental results derived by the transient thermal impedance curve and numerical simulation results based on FEM. The thermal compact model and experimental results could be helpful for modeling of thermal model and heat sink design for such electronic devices.


Author(s):  
Fabien Volle ◽  
Suresh V. Garimella ◽  
Mark A. Juds

Adverse effects of starting-torque transients and high inrush currents in induction motors are typically mitigated by employing electronically controlled soft starting voltages through silicon controlled rectifiers (SCRs). However, the heat dissipation in the soft starter must be carefully managed in the design of motor drives. The objective of this study is to address the heat dissipation in the soft starter by implementing analytical solutions to the heat diffusion equations inside the soft starter. The transient analytical thermal model allows an estimation of the thermal system transfer function from the transient thermal impedance curve, and can be incorporated into a dynamic system model in order to determine the transient performance of a soft starter by evaluating the thyristor junction temperature for different switching time profiles, motor and load combinations, and “ON/OFF” cycles. Predictions from the model are validated by comparing against a coupled thermal and electrical model using a resistance/capacitance network approach.


2019 ◽  
Vol 90 (3) ◽  
pp. 199-203
Author(s):  
A. B. Ershov ◽  
V. Ya. Khorolsky ◽  
I. V. Atanov ◽  
A. V. Efanov

2013 ◽  
Vol 347-350 ◽  
pp. 1630-1634
Author(s):  
Xiao Ming Ding ◽  
Gang Chen ◽  
Dian Li Wang

Wherever possible, we have adopted the newest modern technology. The Au-Si binary alloy sintered chips are silicon or silicon carbide power devices. The sintered temperature is 380 to 390 °C. Using micro-infrared thermal image instrument, compares the microwave transient infrared thermal image test results of sample devices which chips welded process under two different process condition. Measured results show that the thermal resistance after chip welded process optimized is twenty percent smaller than before. It describes the importance of controlling the chip welded process parameters during assembly.


Author(s):  
Kenneth H. Downing

Three-dimensional structures of a number of samples have been determined by electron crystallography. The procedures used in this work include recording images of fairly large areas of a specimen at high tilt angles. There is then a large defocus ramp across the image, and parts of the image are far out of focus. In the regions where the defocus is large, the contrast transfer function (CTF) varies rapidly across the image, especially at high resolution. Not only is the CTF then difficult to determine with sufficient accuracy to correct properly, but the image contrast is reduced by envelope functions which tend toward a low value at high defocus.We have combined computer control of the electron microscope with spot-scan imaging in order to eliminate most of the defocus ramp and its effects in the images of tilted specimens. In recording the spot-scan image, the beam is scanned along rows that are parallel to the tilt axis, so that along each row of spots the focus is constant. Between scan rows, the objective lens current is changed to correct for the difference in specimen height from one scan to the next.


2008 ◽  
Vol 600-603 ◽  
pp. 895-900 ◽  
Author(s):  
Anant K. Agarwal ◽  
Albert A. Burk ◽  
Robert Callanan ◽  
Craig Capell ◽  
Mrinal K. Das ◽  
...  

In this paper, we review the state of the art of SiC switches and the technical issues which remain. Specifically, we will review the progress and remaining challenges associated with SiC power MOSFETs and BJTs. The most difficult issue when fabricating MOSFETs has been an excessive variation in threshold voltage from batch to batch. This difficulty arises due to the fact that the threshold voltage is determined by the difference between two large numbers, namely, a large fixed oxide charge and a large negative charge in the interface traps. There may also be some significant charge captured in the bulk traps in SiC and SiO2. The effect of recombination-induced stacking faults (SFs) on majority carrier mobility has been confirmed with 10 kV Merged PN Schottky (MPS) diodes and MOSFETs. The same SFs have been found to be responsible for degradation of BJTs.


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