Modeling of the impact of source/drain regions on short channel effects in MOSFETs

In this paper, first, the impact of different gate arrangements on the short-channel effects of carbon nanotube field-effect transistors with doped source and drain with the self-consistent solution of the three-dimensional Poisson equation and the Schr¨odinger equation with open boundary conditions, within the non-equilibrium Green function, is investigated. The results indicate that the double-gate structure possesses a quasi-ideal subthreshold oscillation and an acceptable decrease in the drain induced barrier even for a relatively thick gate oxide (5 nm). Afterward, the electrical characteristics of the double-gate carbon nanotube field-effect transistors (DG-CNTFET) are investigated. The results demonstrate that an increase in diameter and density of the nanotubes in the DG-CNTFET increases the on-state current. Also, as the drain voltage increases, the off-state current of the DG-CNTFET decreases. In addition, regarding the negative gate voltages, for a high drain voltage, increasing in the drain current due to band-to-band tunnelling requires a larger negative gate voltage, and for a low drain voltage, resonant states appear

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Impact of multiple channels on the Characteristics of Rectangular GAA MOSFET

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v7i4.pp1899-1905 ◽

2017 ◽

Vol 7 (4) ◽

pp. 1899

Author(s):

Mohammed Khaouani ◽

Ahlam Guen-Bouazza

Keyword(s):

Single Channel ◽

Numerical Study ◽

Drain Current ◽

Short Channel Effects ◽

Short Channel ◽

Channel One ◽

A Value ◽

Device Structures ◽

Channel Effects ◽

The Impact

Square gate all around MOSFETs are a very promising device structures allowing to continue scaling due to their superior control over the short channel effects. In this work a numerical study of a square structure with single channel is compared to a structure with 4 channels in order to highlight the impact of channels number on the device’s DC parameters (drain current and threshold voltage). Our single channel rectangular GAA MOSFET showed reasonable ratio Ion/Ioff of 104, while our four channels GAA MOSFET showed a value of 103. In addition, a low value of drain induced barrier lowering (DIBL) of 60mV/V was obtained for our single channel GAA and a lower value of with 40mv/v has been obtained for our four channel one. Also, an extrinsic transconductance of 88ms/µm have been obtained for our four channels GAA compared to the single channel that is equal to 7ms/µm.

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Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs)

Superlattices and Microstructures ◽

10.1016/j.spmi.2015.06.004 ◽

2015 ◽

Vol 85 ◽

pp. 357-369 ◽

Cited By ~ 32

Author(s):

Vadthiya Narendar ◽

R.A. Mishra

Keyword(s):

Modeling And Simulation ◽

Analytical Modeling ◽

Short Channel Effects ◽

Short Channel ◽

High K ◽

Channel Effects ◽

The Impact

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The impact of stress-induced defects on MOS electrostatics and short-channel effects

Solid-State Electronics ◽

10.1016/j.sse.2014.07.018 ◽

2015 ◽

Vol 103 ◽

pp. 167-172 ◽

Cited By ~ 3

Author(s):

Ivan S. Esqueda

Keyword(s):

Short Channel Effects ◽

Short Channel ◽

Channel Effects ◽

Induced Defects ◽

The Impact

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ANALYSIS OF SHORT CHANNEL EFFECTS IN NANOSCALE MOSFETS

International Journal of Nanoscience ◽

10.1142/s0219581x11007910 ◽

2011 ◽

Vol 10 (01n02) ◽

pp. 275-278 ◽

Cited By ~ 6

Author(s):

GARIMA JOSHI ◽

AMIT CHOUDHARY

Keyword(s):

Quantum Mechanical ◽

Clear Understanding ◽

Short Channel Effects ◽

Carrier Distribution ◽

Short Channel ◽

Threshold Voltage Shift ◽

Channel Effects ◽

Nanoscale Mosfets ◽

Technology Nodes ◽

The Impact

A quantum-mechanical model, by combining the quantum mechanical carrier distribution and short channel effects (SCEs) with the classical carrier transport is used to predict the I–V characteristics at sub-90 nm technology nodes. I–V characteristics of 90, 65, and 45 nm for developed model are benchmarked. The analysis of SCEs, namely, velocity saturation, mobility degradation, and threshold voltage shift, has been carried out in this paper for these technology nodes. The detailed physical view of the variation of these effects with channel length (L) and drain voltage (Vds) has been presented. Also, the impact of including these effects in I–V equations of nanoscale MOSFETs is included in the paper. The observations presented in this paper will help in developing a clear understanding of physical behavior of nanoscale MOSFETs.

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THE IMPACT OF CHANNEL ENGINEERING ON SHORT CHANNEL BEHAVIOR OF NANO FIN-FETs

International Journal of Nanoscience ◽

10.1142/s0219581x12500214 ◽

2012 ◽

Vol 11 (02) ◽

pp. 1250021

Author(s):

RITI KUMARI ◽

MANISH GOSWAMI ◽

B. R. SINGH

Keyword(s):

Concentration Profile ◽

Doping Concentration ◽

Short Note ◽

Short Channel Effects ◽

Short Channel ◽

Channel Engineering ◽

Channel Effects ◽

Uniform Channel ◽

The Impact ◽

Optimum Doping Concentration

This short note presents the simulation result on the effect of channel engineering i.e., non-uniform channel doping on short channel effects (SCE) in nano Fin-FET devices using Silvaco TCAD tool. The nano Fin-FET structures were generated using DEVEDIT and the effect of channel doping concentration has been studied. The optimum doping concentration profile has been observed to considerably improve the SCE in general and drain induced barrier lowering (DIBL) in particular.

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The Carbon Co-implant with Spike RTA Solution for Phosphorus Extension

MRS Proceedings ◽

10.1557/proc-0912-c01-06 ◽

2006 ◽

Vol 912 ◽

Cited By ~ 7

Author(s):

Bartek Pawlak ◽

Ray Duffy ◽

Emmanuel Augendre ◽

Simone Severi ◽

Tom Janssens ◽

...

Keyword(s):

Rapid Thermal Annealing ◽

Successful Implementation ◽

Gate Length ◽

Short Channel Effects ◽

Mos Transistors ◽

Short Channel ◽

Mos Devices ◽

Channel Effects ◽

20 Nm ◽

The Impact

AbstractAs extensions have been up till now always used in N-MOS transistors with an activation anneal. Here, we show that also alternative doping by P can result in junction extensions that are extremely abrupt and shallow thus suitable for upcoming transistor technologies. P extensions are manufactured by amorphization, carbon co-implantation and conventional rapid thermal annealing (RTA). The impact of Si interstitials (Sii) flux suppression on the formation of P junction extensions during RTA is demonstrated. We have concluded that optimization of implants followed by RTA spike offers excellent extensions with depth Xj = 20 nm (taken at 5 × 1018 at./cm3), abruptness 3 nm/dec. and Rs = 326 Ω. Successful implementation of these junctions is straightforward for N-MOS devices with 30 nm gate length and results in an improved short channel effects with respect to the As reference.

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A Temperature-Dependent Threshold Voltage Model for SiGe Source/Drain Si–NT JLFET

10.21467/proceedings.114.59 ◽

2021 ◽

Author(s):

Anchal Thakur ◽

Rohit Dhiman

Keyword(s):

Threshold Voltage ◽

Computer Aided Design ◽

Short Channel Effects ◽

Temperature Dependent ◽

Short Channel ◽

Channel Effects ◽

Aided Design ◽

The Impact ◽

Silicon Nanotube ◽

Threshold Voltage Model

In this paper, we investigate the impact of temperature on threshold voltage in the SiGe source/drain silicon-nanotube junctionless field effect transistor (NT JLFET). A threshold voltage model has been derived with inclusion of temperature for presented device. It is found that when the temperature increases from T = 300 K, T = 400 K, and T = 500 K, the strain produced by the SiGe source/drain on channel has been relaxed. However, the elevated temperature decreases the potential and the electric field in channel due to increases in intrinsic carrier concentration which further shifts the Fermi level towards the band gap. It has been evaluating that the threshold voltage roll-off and the short channel effects increases due to increases in temperature. The numerical results of threshold voltage model have been well compared with results of 2-D technology computer aided design (TCAD) simulations.

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Effect of Negative Capacitance in Partially Ground Plane based SELBOX FET on Capacitance Matching and SCEs

10.21203/rs.3.rs-222107/v1 ◽

2021 ◽

Author(s):

Shalini Chaudhary ◽

Basudha Dewan ◽

Chitrakant Sahu ◽

Menka Yadav

Keyword(s):

Ground Plane ◽

Dielectric Materials ◽

Ferroelectric Material ◽

Negative Capacitance ◽

Short Channel Effects ◽

Short Channel ◽

Channel Effects ◽

Simulation Results ◽

High Dielectric ◽

The Impact

Abstract Here in, we investigated the impact of negative capacitance in PGP-SELBOX NCFET (partial ground plane on a selective buried oxide in negative capacitance FET) over FDSOI. The ferro-electric layer is placed in the gate stack of PGP-SELBOX NCFET to generate the negative capacitance phenomenon. Ferroelectric(FE) materials are similar to dielectric materials but differ in terms of their polarization properties. FE-HFO 2 is used as ferroelectric material due to its sufficient polarization rate with high dielectric capacitance and better reliability. The effect of ferro-electric material parameters like coercive field(E c ) and remnant polarization(P R ) on the capacitance matching of NCFET are analyzed. The simulation results reveal that the R PE factor, which is the ratio of P R to E c , is closely related to better capacitance matching. In addition, the effect of variation in thickness of ferro-electric layer on the average sub-threshold swing(SS) is also explored. The relation between short channel effects ( V th rolloff and DIBL) and thickness of the ferro-electric (t fe ) for PGP-SELBOX NCFET is also analyzed. The simulation results clearly show that PGP-SELBOX NCFET is having reduced SCEs and 10 3 times better II OFF ON ratio over FDSOI NCFET. For optimized value of ferroelectric parameters average SS for proposed device is found as 50 mV/decade at t fe = 5nm which is lesser than FDSOI NCFET ( 56 mV/decade)

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