A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

2012 ◽  
Author(s):  
C. Auth ◽  
C. Allen ◽  
A. Blattner ◽  
D. Bergstrom ◽  
M. Brazier ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Cmos Technology ◽  
High Density ◽  
Fully Depleted ◽  
Low Power Cmos ◽  
Mim Capacitors

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

Planar fully depleted SOI technology: The convergence of high performance and low power towards multimedia mobile applications

2012 ◽  
Author(s):  
Bertrand Pelloux-Prayer ◽  
Milovan Blagojevic ◽  
Olivier Thomas ◽  
Amara Amara ◽  
Andrei Vladimirescu ◽  
...  
Keyword(s):  
Low Power ◽  
Mobile Applications ◽  
High Performance ◽  
Fully Depleted ◽  
Soi Technology
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