Electronic Implementation of Fractional-Order Newton–Leipnik Chaotic System With Application to Communication

2017 ◽  
Vol 12 (5) ◽  
Author(s):  
Mohammad Rafiq Dar ◽  
Nasir Ali Kant ◽  
Farooq Ahmad Khanday
Keyword(s):  
Fractional Order ◽  
Chaotic System ◽  
Chaotic Behavior ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Transconductance Amplifier ◽  
Theoretical Predictions ◽  
On Chip ◽  
System Order

A complementary metal oxide semiconductor-operational transconductance amplifier (CMOS-OTA)-based implementation of fractional-order Newton–Leipnik chaotic system is introduced in this paper. The proposed circuit offers the advantages of electronic tunability of system order and on-chip integration due to MOS only design. The double strange attractor chaotic behavior of the system in consideration for an order of 2.9 has been demonstrated, and effectiveness of this chaotic system in preliminary secure message communication has also been presented. The theoretical predictions of the proposed implementation have been verified by hspice simulator using Austrian Microsystem (AMS) 0.35 μm CMOS process and subsequently compared with matlab simulink results. The power consumption of the system was 103.6 μW for standalone Newton–Leipnik chaotic generator.

Realization of Fractional-Order Double-Scroll Chaotic System Using Operational Transconductance Amplifier (OTA)

2017 ◽  
Vol 27 (01) ◽  
pp. 1850006 ◽  
Author(s):  
Mohammad Rafiq Dar ◽  
Nasir Ali Kant ◽  
Farooq Ahmad Khanday
Keyword(s):  
Fractional Order ◽  
Chaotic System ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Operational Transconductance Amplifiers ◽  
System A ◽  
Transconductance Amplifier ◽  
Theoretical Predictions

Realization of fractional-order double-scroll chaotic system using Operational Transconductance Amplifiers (OTAs) as active elements are presented in this paper. The fractional-order double-scroll chaotic system has been studied before as well using passive RC-ladder and tree-based structures but in this paper the requisite fractional-order integration has been accomplished through an integer-order multiple-feedback topology. As compared to double or multiple scroll chaotic systems existing in the open literature, the proposed realization offers the advantages of (a) low-voltage implementation, (b) integrablity as the design is resistor- and inductor-less and only grounded components have been employed in the design, and, (c) electronic tunability of the fractional order, time-constants and gain factors. In order to demonstrate the usefulness of the chaotic system, a simple secure message communication system has been designed and verified for its operation. The theoretical predictions of the proposed implementations have been verified by using 0.35[Formula: see text][Formula: see text]m complementary metal oxide semiconductor (CMOS) process file provided by Austrian Micro System (AMS).

scholarly journals High PSRR Wide Supply Range Dual-Voltage Reference Circuit for Bio-Implantable Applications

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 2024
Author(s):  
Ruhaifi Bin Abdullah Zawawi ◽  
Hojong Choi ◽  
Jungsuk Kim
Keyword(s):  
Capacitor Bank ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Voltage Reference ◽  
Current Compensation ◽  
Fully Integrated ◽  
Reference Circuit ◽  
On Chip

On-chip systems are challenging owing to the limited size of the components, such as the capacitor bank in the rectifier. With a small on-chip capacitor, the output voltage of the rectifier might ring if the circuit experiences significant changes in current. The reference circuit is the first block after the rectifier, and the entire system relies on its robustness. A fully integrated dual-voltage reference circuit for bio-implantable applications is presented. The proposed circuit utilizes nonlinear current compensation techniques that significantly decrease supply variations and reject high-supply ripples for various frequencies. The reference circuit was verified using a 0.35 µm complementary metal-oxide semiconductor (CMOS) process. Maximum PSRR values of −112 dB and −128 dB were obtained. With a supply range from 2.8 to 12 V, the proposed design achieves 0.916 and 1.5 mV/V line regulation for the positive and negative reference circuits, respectively.

Realization of Integrable Incommensurate-Fractional-Order-Rössler-System Design Using Operational Transconductance Amplifiers (OTAs) and Its Experimental Verification

2017 ◽  
Vol 27 (05) ◽  
pp. 1750077 ◽  
Author(s):  
Mohammad Rafiq Dar ◽  
Nasir Ali Kant ◽  
Farooq Ahmad Khanday
Keyword(s):  
Fractional Order ◽  
Low Voltage ◽  
Chaotic Behavior ◽  
Vlsi Design ◽  
Cmos Process ◽  
Operational Transconductance Amplifiers ◽  
Rossler System ◽  
Theoretical Predictions ◽  
Rössler System ◽  
Transconductance Amplifiers

In this paper, electronic implementation of fractional-order Rössler system using operational transconductance amplifiers (OTAs) is presented which until now was only being investigated through numerical simulations. The realization offers the benefits of low-voltage implementation, integrability and electronic tunability. In addition, the proposed circuit is a MOS only design (as no BJTs have been used) which contains only grounded components and is therefore suitable for monolithic VLSI design. The chaotic behavior of the fractional-order Rössler system in consideration with the incommensurate orders has been demonstrated which finds many applications in several fields. The theoretical predictions of the proposed implementation have been verified through experimentation and HSPICE simulator using Austrian Micro System (AMS) 0.35[Formula: see text][Formula: see text]m CMOS process and the obtained results have been found in good agreement with the Matlab simulink theoretical results obtained using FOMCON simulink toolbox. Besides, a secure message communication system has been considered to demonstrate fully the usefulness of the chaotic system.

scholarly journals A Terahertz CMOS V-Shaped Patch Antenna with Defected Ground Structure

Sensors ◽  
2018 ◽  
Vol 18 (8) ◽  
pp. 2432 ◽  
Author(s):  
Hyeongjin Kim ◽  
Wonseok Choe ◽  
Jinho Jeong
Keyword(s):  
Radiation Resistance ◽  
Patch Antenna ◽  
Impedance Matching ◽  
Ground Plane ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Defected Ground Structure ◽  
Ground Structure ◽  
On Chip

In this paper, a V-shaped patch antenna with defected ground structure is proposed at terahertz to overcome the limited performance of a standard complementary metal-oxide semiconductor (CMOS) patch antenna consisting of several metal layers and very thin interdielectric layers. The proposed V-shaped patch with slots allows the increased radiation resistance and broadband performance. In addition, the patch resonating at different frequency from the V-shaped patch is stacked on the top to broaden the impedance-matching bandwidth. More importantly, the slots are formed in the ground plane, which is called the defected ground structure, to further increase the radiation resistance and thus improve the bandwidth and efficiency. It is verified from electromagnetic simulations that the leakage waves from the defected ground can enhance the antenna directivity and gain by coherently interfering with the topside radiation. The proposed on-chip antenna is fabricated using a standard 65 nm CMOS process. The on-wafer measurement shows very wide bandwidth in input reflection coefficient (<−10 dB), greater than 28.7% from 240 to >320 GHz. The measured peak gain was as high as 5.48 dBi at 295 GHz. To the best of the authors’ knowledge, these results belong to the best performance among the terahertz CMOS on-chip antennas without using additional components or processes such as dielectric resonators, lens, or substrate thinning.

scholarly journals Phase Change Metasurfaces by Continuous or Quasi-Continuous Atoms for Active Optoelectronic Integration

Materials ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 1272
Author(s):  
Zhihua Fan ◽  
Qinling Deng ◽  
Xiaoyu Ma ◽  
Shaolin Zhou
Keyword(s):  
Phase Change ◽  
Phase Change Materials ◽  
Complementary Metal Oxide Semiconductor ◽  
Photonic Devices ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Nanophotonic Devices ◽  
Optoelectronic Integration ◽  
Hybrid Devices ◽  
Micro Electromechanical System

In recent decades, metasurfaces have emerged as an exotic and appealing group of nanophotonic devices for versatile wave regulation with deep subwavelength thickness facilitating compact integration. However, the ability to dynamically control the wave–matter interaction with external stimulus is highly desirable especially in such scenarios as integrated photonics and optoelectronics, since their performance in amplitude and phase control settle down once manufactured. Currently, available routes to construct active photonic devices include micro-electromechanical system (MEMS), semiconductors, liquid crystal, and phase change materials (PCMs)-integrated hybrid devices, etc. For the sake of compact integration and good compatibility with the mainstream complementary metal oxide semiconductor (CMOS) process for nanofabrication and device integration, the PCMs-based scheme stands out as a viable and promising candidate. Therefore, this review focuses on recent progresses on phase change metasurfaces with dynamic wave control (amplitude and phase or wavefront), and especially outlines those with continuous or quasi-continuous atoms in favor of optoelectronic integration.

scholarly journals Universal Filter Based on Compact CMOS Structure of VDDDA

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1683
Author(s):  
Winai Jaikla ◽  
Fabian Khateb ◽  
Tomasz Kulej ◽  
Koson Pitaksuttayaprot
Keyword(s):  
Metal Oxide ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Experimental Results ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Voltage Gain ◽  
Universal Filter ◽  
Mos Transistor

This paper proposes the simulated and experimental results of a universal filter using the voltage differencing differential difference amplifier (VDDDA). Unlike the previous complementary metal oxide semiconductor (CMOS) structures of VDDDA that is present in the literature, the present one is compact and simple, owing to the employment of the multiple-input metal oxide semiconductor (MOS) transistor technique. The presented filter employs two VDDDAs, one resistor and two grounded capacitors, and it offers low-pass: LP, band-pass: BP, band-reject: BR, high-pass: HP and all-pass: AP responses with a unity passband voltage gain. The proposed universal voltage mode filter has high input impedances and low output impedance. The natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain. For a BP filter, the root mean square (RMS) of the equivalent output noise is 46 µV, and the third intermodulation distortion (IMD3) is −49.5 dB for an input signal with a peak-to peak of 600 mV, which results in a dynamic range (DR) of 73.2 dB. The filter was designed and simulated in the Cadence environment using a 0.18-µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). In addition, the experimental results were obtained by using the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental one that confirmed the advantages of the filter.

Millimeter-wave dual-mode and dual-band switchable Gilbert up-conversion mixer in 65-nm CMOS process

2021 ◽  
pp. 1-5
Author(s):  
Fang Zhu ◽  
Guo Qing Luo
Keyword(s):  
Millimeter Wave ◽  
Complementary Metal Oxide Semiconductor ◽  
Local Oscillator ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Dual Band ◽  
Cmos Process ◽  
Pumping Power ◽  
Dual Mode ◽  
Dc Power

Abstract In this paper, a millimeter-wave (MMW) dual-mode and dual-band switchable Gilbert up-conversion mixer in a commercial 65-nm complementary metal oxide semiconductor (CMOS) process is presented. By simply changing the bias, the proposed CMOS Gilbert up-conversion mixer can be switched between subharmonic and fundamental operation modes for MMW dual-band applications. With a low local oscillator pumping power of 3 dBm and low dc power consumption of 6 mW, the proposed CMOS Gilbert up-conversion mixer exhibits a measured conversion gain of −0.5 ± 1.5 dB from 37 to 50 GHz and 2.5 ± 1.5 dB from 17.5 to 32 GHz for the subharmonic and fundamental modes, respectively.

scholarly journals Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 369 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Nikos Mastorakis
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Performance Comparison ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Design Metrics ◽  
Ripple Carry Adder ◽  
Speed Performance

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

Review: Static and Dynamic Analysis Methods for Multi-Branch Biasing Circuits

2018 ◽  
Vol 27 (13) ◽  
pp. 1830008
Author(s):  
Jin Wu ◽  
Pengfei Dai ◽  
Jie Peng ◽  
Lixia Zheng ◽  
Weifeng Sun
Keyword(s):  
Feedback Loop ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Critical Parameters ◽  
Cmos Process ◽  
Stable Equilibrium Point ◽  
Static And Dynamic Analysis ◽  
Text Structures ◽  
Different Types

The fundamental theories and primary structures for the multi-branch self-biasing circuits are reviewed in this paper. First, the [Formula: see text]/[Formula: see text] and [Formula: see text]/[Formula: see text] structures illustrating the static current definition mechanism are presented, including the conditions of starting up and entering into a stable equilibrium point. Then, the AC method based on the loop gain evaluation is utilized to analyze different types of circuits. On this basis, the laws which can couple the branches of self-biasing circuits to construct a suitable close feedback loop are summarized. By adopting Taiwan Semiconductor Manufacturing Company (TSMC)’s 0.18[Formula: see text][Formula: see text]m complementary metal–oxide–semiconductor (CMOS) process with 1.8[Formula: see text][Formula: see text] supply voltage, nearly all the circuits mentioned in the paper are simulated in the same branch current condition, which is close to the corresponding calculated results. Therefore, the methods summarized in this paper can be utilized for distinguishing, constructing, and optimizing critical parameters for various structures of the self-biasing circuits.

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