An Integrated Nano-Structured Heat Spreader for High Heat Flux Electronic Systems

Author(s):  
Siddharth Bhopte ◽  
Seshu B. Desu ◽  
Bahgat Sammakia

With the increase in power densities and decrease in chip and electronic package dimensions, their thermal management is a challenge and is a focus of several ongoing research efforts. To achieve the desired thermal management for optimal device operation, heat generated by the chip has to be effectively transferred to the ambient via several structures of the electronic package. Hence the need for development of high thermal conductivity structures is of prime importance. Heat spreaders quickly spread the heat generated by the chips over a larger area from where it is conducted to the ambient via heat sink. Heat-spreading research from a materials view point involves direct combination of high thermal conductivity materials within the microprocessor substrate. In this paper, a novel nano heat spreader design is proposed. Highly conductive graphene layer is integrated on a silicon carbide substrate on one side and thin films of carbon nano tubes as thermal interface material on the other side. Analytical solutions and case studies are presented to show that the proposed approach for the heat spreader design can yield very high effective thermal conductivity while remaining mechanically flexible, as required for reducing thermal stresses.

Author(s):  
David Shaddock ◽  
Stanton Weaver ◽  
Ioannis Chasiotis ◽  
Binoy Shah ◽  
Dalong Zhong

The power density requirements continue to increase and the ability of thermal interface materials has not kept pace. Increasing effective thermal conductivity and reducing bondline thickness reduce thermal resistance. High thermal conductivity materials, such as solders, have been used as thermal interface materials. However, there is a limit to minimum bondline thickness in reducing resistance due to increased fatigue stress. A compliant thermal interface material is proposed that allows for thin solder bondlines using a compliant structure within the bondline to achieve thermal resistance <0.01 cm2C/W. The structure uses an array of nanosprings sandwiched between two plates of materials to match thermal expansion of their respective interface materials (ex. silicon and copper). Thin solder bondlines between these mating surfaces and high thermal conductivity of the nanospring layer results in thermal resistance of 0.01 cm2C/W. The compliance of the nanospring layer is two orders of magnitude more compliant than the solder layers so thermal stresses are carried by the nanosprings rather than the solder layers. The fabrication process and performance testing performed on the material is presented.


Author(s):  
Jie Wei

Cooling technologies for dealing with high-density and asymmetric power dissipation are discussed, arising from thermal management of high performance server CPU-packages. In this paper, investigation and development of associated technologies are introduced from a viewpoint of industrial application, and attention is focused on heat conduction and removal at the package and heatsink module level. Based on analyses of power dissipation and package cooling characteristics, properties of a new metallic thermal interface material are presented where the Indium-Silver composite was evaluated for integrating the chip and its heat-spreader, effects of heat spreading materials on package thermal performance are investigated including high thermal conductivity diamond composites, and evaluations of enhanced heatsink cooling capability are illustrated where high thermal conductivity devices of heat pipes or vapor chambers were applied for improving heat spreading in the heatsink base.


Author(s):  
Minhua Lu ◽  
Larry Mok ◽  
R. J. Bezama

A vapor chamber using high thermal conductivity and permeability graphite foam as a wick has been designed, built and tested. With ethanol as the working fluid, the vapor chamber has been demonstrated at a heat flux of 80 W/cm2. The effects of the capillary limit, the boiling limit, and the thermal resistance in restricting the overall performance of a vapor chamber have been analyzed. Because of the high thermal conductivity of the graphite foams, the modeling results show that the performance of a vapor chamber using a graphite foam is about twice that of one using a copper wick structure. Furthermore, if water is used as the working fluid instead of ethanol, the performance of the vapor chamber will be increased further. Graphite foam vapor chambers with water as the working fluid can be made by treating the graphite foam with an oxygen plasma to improve the wetting of the graphite by the water.


2005 ◽  
Vol 128 (2) ◽  
pp. 125-129
Author(s):  
Sadegh M. Sadeghipour ◽  
Mehdi Asheghi

Lack of an efficient thermal management strategy and system can often lead to overall system failure in advanced microprocessors. This can be avoided by utilization of the high thermal conductivity materials, as heat spreader/sink, in compact packaging systems. The diamondlike dielectric materials, such as diamond, silicon nitride (Si3N4), aluminum nitride (AlN), silicon carbide (SiC), etc., are the likely choices. However, thermal characterization of such high thermal conductivity materials has proven to be challenging due to variations in the fabrication processes and, therefore, their microstructures as well as the practical difficulties in measuring small temperature gradients during the characterization. In this paper, we will report on a novel film on substrate technique that can be used conveniently for repeated measurements of the lateral thermal conductivity of the high thermal conductivity film layers, with thicknesses between 100 and 500μm.


Author(s):  
Hafez Raeisi Fard ◽  
Kamyar Pashayi ◽  
Fengyuan Lai ◽  
Joel Plawsky ◽  
Theodorian Borca-Tasciuc

Fast and efficient exchange of thermal energy plays a vital role in the thermal management of electronic and optoelectronic devices. A critical component for thermal management is a thermal interface material (TIM) that is used to minimize the contact thermal resistance between surfaces and to provide a low resistance pathway to spread and remove heat. Ideal TIMs must pass several key requirements: 1) high thermal conductivity κ and low thermal contact resistance with the mating surfaces; 2) easy to apply with controlled thickness; 3) low temperature processing; 4) able to accommodate thermally induced mechanical stresses during on-off cycling of the device1. Particle-based composites have reasonable slurry viscosities, however their thermal conductivity are usually very low (<10 Wm−1K−1), even when high κ nanofillers are employed, due to the thermal interface resistance between nanoparticles and the polymer matrix2 or the absence of high κ pathways.


Author(s):  
Patrick A. Coico ◽  
Gaetano Messina ◽  
Steven Ostrander ◽  
Jeffrey Zitz ◽  
Wei Zou

The large Multi-Chip Modules (MCM) used in the IBM p-Server computer systems, and their predecessors, have required rather unique cooling solutions and module hardware designs in order to meet the thermal, mechanical and reliability requirements placed on the package. The module internal thermal solution has evolved from a spring-loaded metal contact technology to a thermal compound based design using a novel gap adjustment technology employing a soldered conduction component. This current MCM makes use of a novel technology called Small Gap Technology (SGT). This technique makes it possible to control thermal compound interface thicknesses or gaps to a very tight tolerance from chip-to-chip and module-to-module. Heat flux values that have been handled vary from approximately 20 to 53 W/cm2 depending on the type of chip and the system performance level. Even higher heat fluxes have been projected for next generation products. The hardware and processing techniques employed to manufacture these modules are quite unique. These products are typically on the order of 100mm chip carrier size or 140mm overall module footprint on a side (approximately 90 cm2 of carrier area) and contain 8 chips and numerous discrete devices. The process fixturing and equipment must be able to handle the relatively large thermal mass of the components. The sequence of processing steps must take into account limitations on the material properties of the various module components. This paper will describe the SGT thermal management solution. The hardware and process employed to make the gap adjustments and the thermal interface material used in these high heat flux applications will be discussed. In addition, supporting thermal/mechanical modelling, thermal performance data and reliability data will be presented.


Author(s):  
Gary L. Solbrekken

Localized areas of high heat flux on microprocessors are currently being identified as a dominant challenge for the thermal management community. Heat flux values up to 1 kW/cm2 prevailing over a fraction of the overall CPU surface area create local hot spots that need to be cooled. However, thermal solutions designed for the maximum heat flux overcool the rest of the CPU, wasting resources and creating large on-die temperature gradients. Wasting resources obviously has a negative economic and thermodynamic impact. However, it has been argued that large on-die temperature gradients reduce chip reliability and increase the difficulty in laying out the electric circuits. The current study proposes a strategy to reduce local hot spots by enhancing heat spreading through the use of the Peltier effect. The Peltier effect is most commonly associated with the operation of thermoelectric modules. In thermoelectric modules, heat is transported across the module by electrons. Ideally, the material used for the thermoelectric module would have a very low thermal conductivity to reduce the amount of back heat conduction through the thermoelectric elements, and the electric resistivity would be very low to minimize the Joule heating. Using today’s best commercially available thermoelectric materials, the thermal conductivity, electric resistivity, and Seebeck coefficient are such that the COP for the thermoelectric module is on the order of 1. This implies that in order to cool a processor dissipating 100W, an additional 100W of electric power must be supplied to the thermoelectric module. A total of 200W must then be rejected by the heat sink and any building HVAC system. A more pragmatic approach is to use the Peltier effect to not cool the entire CPU, but rather only the high heat flux region. This is accomplished by placing the thermoelectric elements laterally on the backside of the CPU. The cooling junction is placed in the proximity of the high flux region, while the heating junction is placed in contact with the CPU in low heat flux area that can tolerate the additional heat, effectively creating an active heat spreader. The Peltier enhanced heat spreading proposed here is shown to provide a reduction in the temperature of a localized hot spot relative to passive heat spreading. The amount of reduction in temperature depends on the thickness of the material as well as the thermal conductivity, but values up to 50% are illustrated.


2015 ◽  
Vol 137 (3) ◽  
Author(s):  
Abas Abdoli ◽  
George S. Dulikravich ◽  
Genesis Vasquez ◽  
Siavash Rastkar

Two-layer single phase flow microchannels were studied for cooling of electronic chips with a hot spot. A chip with 2.45 × 2.45 mm footprint and a hot spot of 0.5 × 0.5 mm in its center was studied in this research. Two different cases were simulated in which heat fluxes of 1500 W cm−2 and 2000 W cm−2 were applied at the hot spot. Heat flux of 1000 W cm−2 was applied on the rest of the chip. Each microchannel layer had 20 channels with an aspect ratio of 4:1. Direction of the second microchannel layer was rotated 90 deg with respect to the first layer. Fully three-dimensional (3D) conjugate heat transfer analysis was performed to study the heat removal capacity of the proposed two-layer microchannel cooling design for high heat flux chips. In the next step, a linear stress analysis was performed to investigate the effects of thermal stresses applied to the microchannel cooling design due to variations of temperature field. Results showed that two-layer microchannel configuration was capable of removing heat from high heat flux chips with a hot spot.


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