Analysis and Design of Electrothermal Actuators Fabricated From Single Crystal Silicon

2000 ◽  
Author(s):  
John M. Maloney ◽  
Don L. DeVoe ◽  
David S. Schreiber

Abstract Thermal actuators that deflect laterally by resistive heating have been fabricated in single crystal silicon (SCS) by deep reactive ion etching (DRIE). With heights of 50 μm, these high-aspect actuators produce significantly larger forces than similar polysilicon devices. Problems with stiction are also avoided through the use of silicon-on-insulator (SOI) technology. An analytical model is applied to U-beam and V-beam actuator shapes fabricated on SOI wafers. The electrothermal component of the analysis uses an axial conduction model to predict temperature distribution; the thermomechanical component employs elastic beam theory to calculate deflection due to thermal strain. Experimental results are compared to analytical predictions. Deflections of 29 μm for a 1200 μm long, 12 μm wide V-beam actuator were observed, corresponding to a predicted force of 7.6 mN.

Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.


Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1118
Author(s):  
Yuan Tian ◽  
Yi Liu ◽  
Yang Wang ◽  
Jia Xu ◽  
Xiaomei Yu

In this paper, a polyimide (PI)/Si/SiO2-based piezoresistive microcantilever biosensor was developed to achieve a trace level detection for aflatoxin B1. To take advantage of both the high piezoresistance coefficient of single-crystal silicon and the small spring constant of PI, the flexible piezoresistive microcantilever was designed using the buried oxide (BOX) layer of a silicon-on-insulator (SOI) wafer as a bottom passivation layer, the topmost single-crystal silicon layer as a piezoresistor layer, and a thin PI film as a top passivation layer. To obtain higher sensitivity and output voltage stability, four identical piezoresistors, two of which were located in the substrate and two integrated in the microcantilevers, were composed of a quarter-bridge configuration wheatstone bridge. The fabricated PI/Si/SiO2 microcantilever showed good mechanical properties with a spring constant of 21.31 nN/μm and a deflection sensitivity of 3.54 × 10−7 nm−1. The microcantilever biosensor also showed a stable voltage output in the Phosphate Buffered Saline (PBS) buffer with a fluctuation less than 1 μV @ 3 V. By functionalizing anti-aflatoxin B1 on the sensing piezoresistive microcantilever with a biotin avidin system (BAS), a linear aflatoxin B1 detection concentration resulting from 1 ng/mL to 100 ng/mL was obtained, and the toxic molecule detection also showed good specificity. The experimental results indicate that the PI/Si/SiO2 flexible piezoresistive microcantilever biosensor has excellent abilities in trace-level and specific detections of aflatoxin B1 and other biomolecules.


2020 ◽  
pp. 100107
Author(s):  
L.G. Michaud ◽  
E. Azrak ◽  
C. Castan ◽  
F. Fournel ◽  
F. Rieutord ◽  
...  

Author(s):  
Wenjun Liu ◽  
Mehdi Asheghi ◽  
K. E. Goodson

Simulations of the temperature field in Silicon-on-Insulator (SOI) and strained-Si transistors can benefit from experimental data and modeling of the thin silicon layer thermal conductivity at high temperatures. This work presents the first experimental data for 20 and 100 nm thick single crystal silicon layers at high temperatures and develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon-boundary scattering for pure and doped silicon layers. The model applies to temperatures range 300–1000 K for silicon layer thicknesses from 10 nm to 1 μm (and even bulk) and agrees well with the experimental data. In addition, the model has an excellent agreement with the predictions of thin film thermal conductivity based on thermal conductivity integral and Boltzmann transport equation, although it is significantly more robust and convenient for integration into device simulators. The experimental data and predictions are required for accurate thermal simulation of the semiconductor devices, nanostructures and in particular the SOI and strained-Si transistors.


1984 ◽  
Vol 33 ◽  
Author(s):  
P. Zorabedian ◽  
T. I. Kamins

ABSTRACTTwo scanning methods for laterally-seeded recrystallization of striped silicon-on-insulator/seed structures with an elliptical laser beam are discussed. One method requires repeated remelting of the silicon film and is controlled by the temperature of the substrate, which is locally heated by the beam. This method results in very few defects and single-crystal silicon-on-insulator stripes up to 50 μm wide. The second method involves little remelting and is primarily controlled by the lateral offset of the beam with respect to the stripes. Single-crystal silicon-on-insulator stripes up to 40 μm wide have been obtained, with defects consisting primarily of stacking faults and twins, as well as some grain boundaries. These defects show little effect on MOS transistor leakage current.


Author(s):  
Wenhua Zhang ◽  
Weibin Zhang ◽  
Kimberly Turner ◽  
Peter G. Hartwell

We present a single-mask single-crystal silicon (SCS) process for the fabrication of suspended MicroElectroMechanical devices (MEMS). This is a bulk micro-machining process that uses Deep Reactive Ion Etch (DeepRIE) of a silicon-on-insulator (SOI) substrate with highly doped device layer to fabricate movable single-crystal silicon MEMS structures, which can be electrically actuated without metal deposition. The buried oxide layer is not removed afterwards and no wet process release is involved in the whole process sequence, which makes this process different from others works based on SOI wafer. Several MEMS oscillators have been made using this process. Dynamic behavior is characterized using a laser vibrometer. Quality factor is improved by more than 1 order compared to the same oscillator made using SCREAM process.


2014 ◽  
Vol 926-930 ◽  
pp. 881-884
Author(s):  
Qing Hua Chen ◽  
Yan Mei Li ◽  
Ying Jun Chen ◽  
Wen Gang Wu

The two different fabrications of the Micro-Electro-Mechanical Systems (MEMS) mirrors were compared: a single-crystal-silicon (SCS)-based micromachining and a silicon-on-insulator (SOI)- based micromachining. While the SOI parts had significantly smaller curved device appearance, they were outperformed in most areas by the SCS parts. This was due primarily to the smaller stress factor in the device layer in the SOI parts compared to the polysilicon layer used in the SCS parts.


2011 ◽  
Vol 6 (4) ◽  
pp. 240
Author(s):  
Yong Liu ◽  
Gang Zhao ◽  
Baoqing Li ◽  
Li Wen ◽  
Jiaru Chu

2005 ◽  
Vol 128 (1) ◽  
pp. 75-83 ◽  
Author(s):  
Wenjun Liu ◽  
Mehdi Asheghi

Self-heating in deep submicron transistors (e.g., silicon-on-insulator and strained-Si) and thermal engineering of many nanoscale devices such as nanocalorimeters and high-density thermomechanical data storage are strongly influenced by thermal conduction in ultra-thin silicon layers. The lateral thermal conductivity of single-crystal silicon layers of thicknesses 20 and 100nm at temperatures between 30 and 450K are measured using joule heating and electrical-resistance thermometry in suspended microfabricated structures. In general, a large reduction in thermal conductivity resulting from phonon-boundary scattering is observed. Thermal conductivity of the 20nm thick silicon layer at room temperature is nearly 22Wm−1K−1, compared to the bulk value, 148Wm−1K−1. The predictions of the classical thermal conductivity theory that accounts for the reduced phonon mean free paths based on a solution of the Boltzmann transport equation along a layer agrees well with the experimental results.


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