Effects of Corner/Edge Bonding and Underfill Properties on the Thermal Cycling Performance of Lead Free Ball Grid Array Assemblies

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
P. Borgesen ◽  
D. Blass ◽  
M. Meilunas
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Ball Grid Array ◽  
Cycling Performance ◽  
Circuit Board ◽  
Lead Free ◽  
Sac305 Solder ◽  
Solder Balls ◽  
Selection Of

Underfilling will almost certainly improve the performance of an area array assembly in drop, vibration, etc. However, depending on the selection of materials, the thermal fatigue life may easily end up worse than without an underfill. This is even more true for lead free than for eutectic SnPb soldered assemblies. If reworkability is required, the bonding of the corners or a larger part of the component edges to the printed circuit board (PCB), without making contact with the solder joints, may offer a more attractive materials selection. A 30 mm flip chip ball grid array (FCBGA) component with SAC305 solder balls was attached to a PCB and tested in thermal cycling with underfills and corner/edge bonding reinforcements. Two corner bond materials and six reworkable and nonreworkable underfills with a variety of mechanical properties were considered. All of the present underfills reduced the thermal cycling performance, while edge bonding improved it by up to 50%. One set of the FCBGAs was assembled with a SnPb paste and underfilled with a soft reworkable underfill. Surprisingly, this improved the thermal cycling performance slightly beyond that of the nonunderfilled assemblies, providing up to three times better life than for those assembled with a SAC305 paste.

Evaluation of a Conductive Adhesive Based Approach to Lead Free Flip Chip Assembly

2002 ◽  
Author(s):  
Muthiah Venkateswaran ◽  
Peter Borgesen ◽  
K. Srihari
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Critical Evaluation ◽  
Conductive Adhesive ◽  
Circuit Board ◽  
Lead Free ◽  
Conductive Adhesives ◽  
Flip Chip Assembly ◽  
Placement Machine

Electrically conductive adhesives are emerging as a lead free, flux less, low temperature alternative to soldering in a variety of electronics and optoelectronics applications. Some of the potential benefits are obvious, but so far the adhesives have some limitations as well. The present work offers a critical evaluation of one approach to flip chip assembly, which lends itself particularly well to use with a high speed placement machine. Wafers were bumped by stencil printing of a thermoset conductive adhesive, which was then fully cured. In assembly, the conductive adhesive paste was stencil printed onto the pads of a printed circuit board and cured after die placement. The printing process was optimized to ensure robust assembly and the resulting reliability assessed.

Experimental and Numerical Investigation of the Reliability of Double-Sided Area Array Assemblies

2006 ◽  
Vol 128 (4) ◽  
pp. 441-448 ◽  
Author(s):  
S. Chaparala ◽  
J. M. Pitarresi ◽  
S. Parupalli ◽  
S. Mandepudi ◽  
M. Meilunas
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Mirror Image ◽  
Circuit Board ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Area Array ◽  
Plastic Ball

One of the primary advantages of surface mount technology (SMT) over through-hole technology is that SMT allows the assembly of components on both sides of the printed circuit board (PCB). Currently, area array components such as ball grid array (BGA) and chip-scale package (CSP) assemblies are being used in double-sided configurations for network and memory device applications as they reduce the routing space and improve electrical performance (Shiah, A. C., and Zhou, X., 2002, “A Low Cost Reliability Assessment for Double-Sided Mirror-Imaged Flip Chip BGA Assemblies,” Proceedings of the Seventh Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 7–15, and Xie, D., and Yi, S., 2001, “Reliability Design and Experimental work for Mirror Image CSP Assembly”, Proceedings of the International Symposium on Microelectronics, Baltimore, October, pp. 417–422). These assemblies typically use a “mirror image” configuration wherein the components are placed on either side of the PCB directly over each other; however, other configurations are possible. Double-sided assemblies pose challenges for thermal dissipation, inspection, rework, and thermal cycling reliability. The scope of this paper is the study of the reliability of double-sided assemblies both experimentally and through numerical simulation. The assemblies studied include single-sided, mirror-imaged, 50% offset CSP assemblies, CSPs with capacitors on the backside, single-sided, mirror-imaged plastic ball grid arrays (PBGAs), quad flat pack (QFP)/BGA mixed assemblies. The effect of assembly stiffness on thermal cycling reliability was investigated. To assess the assembly flexural stiffness and its effect on the thermal cycling reliability, a three-point bending measurement was performed. Accelerated thermal cycling cycles to failure were documented for all assemblies and the data were used to calculate the characteristic life. In general, a 2X to 3X decrease in reliability was observed for mirror-image assemblies when compared to single-sided assemblies for both BGAs and CSPs on 62mil test boards. The reliability of mirror-image assemblies when one component was an area array device and the other was a QFP was comparable to the reliability of the single-sided area array assemblies alone, that is, the QFP had almost no influence on the double-sided reliability when used with an area array component. Moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux’s crack propagation method.

Causes of Degradation of Thermal Performance of Ball Grid Arrays After Thermal Cycling

2007 ◽  
Author(s):  
Roy W. Knight ◽  
Yasser Elkady ◽  
Jeffrey C. Suhling ◽  
Pradeep Lall
Keyword(s):  
Solder Joint ◽  
Thermal Resistance ◽  
Thermal Cycling ◽  
Thermal Performance ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Element Analysis ◽  
Solder Balls ◽  
Ball Grid Array Packages ◽  
The Impact

The thermal performance of Ball Grid Array packages depends upon many parameters including die size, use of thermal balls, number of perimeter balls, use of underfill, and printed circuit board heat spreader and thermal via design. Thermal cycling can affect the integrity of thermal paths in and around the BGA as a result of the cracking of solder balls and delamination of the package, including at underfill interfaces. In this study, the impact of thermal cycling on the thermal performance of BGA’s was investigated and quantified. A number of test boards which included a range of the parameters cited above were experimentally examined. A baseline thermal resistance was measured for each case, which was verified with numerical thermal modeling. The boards were then subjected to thermal cycling from −40°C to 125°C. Every 250 cycles the thermal performance was measured. Packages expected to be least reliable (with large die and no underfill), showed an increase in thermal resistance after 750 thermal cycles. Further increases in thermal resistance were observed with continuous thermal cycling until solder joint failure occurred at 1250 cycles, preventing additional measurements. Finite element analysis identified critical thermal and perimeter solder balls as the most likely sites for cracking. Boards were cross-sectioned and examined for solder joint cracks and delamination to identify the cause for the observed increases in thermal resistance. Cracking was found in the critical thermal and perimeter solder balls.

Effect of Heat-Spreader Sizes on the Thermal Performance of Large Cavity-Down Plastic Ball Grid Array Packages

1999 ◽  
Vol 121 (4) ◽  
pp. 242-248 ◽  
Author(s):  
J. Lau ◽  
T. Chen ◽  
S.-W. R. Lee
Keyword(s):  
Printed Circuit Board ◽  
Cost Effective ◽  
Ball Grid Array ◽  
Circuit Board ◽  
Cooling Power ◽  
Heat Spreader ◽  
Plastic Ball ◽  
Plastic Ball Grid Array ◽  
Solder Balls ◽  
Ball Grid Array Packages

The effect of heat-spreader sizes on the temperature distribution, thermal resistance, and cooling power of a set of cost-effective cavity-down plastic ball grid array (PBGA) packages assembled on a FR-4 epoxy glass printed circuit board (PCB) is presented. The sizes of these packages are 35 × 35 mm and 40 × 40 mm with 4 and 5 rows of solder balls.

Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint

2004 ◽  
Author(s):  
Norman J. Armendariz ◽  
Prawin Paulraj
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Gold Surface ◽  
Circuit Board ◽  
Lead Free ◽  
Processing Temperature ◽  
The European Union ◽  
Printed Circuit ◽  
Higher Temperature ◽  
Tin Silver Copper

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

scholarly journals Performance of Sn-3.0Ag-0.5Cu Composite Solder with Kaolin Geopolymer Ceramic Reinforcement on Microstructure and Mechanical Properties under Isothermal Ageing

Materials ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 776
Author(s):  
Nur Syahirah Mohamad Zaimi ◽  
Mohd Arif Anuar Mohd Salleh ◽  
Andrei Victor Sandu ◽  
Mohd Mustafa Al Bakri Abdullah ◽  
Norainiza Saud ◽  
...  
Keyword(s):  
Shear Strength ◽  
Composite Solder ◽  
Printed Circuit Board ◽  
Microwave Sintering ◽  
Copper Substrate ◽  
Bulk Diffusion ◽  
Circuit Board ◽  
Sac305 Solder ◽  
Lap Shear ◽  
Isothermal Ageing

This paper elucidates the effect of isothermal ageing at temperature of 85 °C, 125 °C and 150 °C for 100, 500 and 1000 h on Sn-3.0Ag-0.5Cu (SAC305) lead-free solder with the addition of 1 wt% kaolin geopolymer ceramic (KGC) reinforcement particles. SAC305-KGC composite solders were fabricated through powder metallurgy using a hybrid microwave sintering method and reflowed on copper substrate printed circuit board with an organic solderability preservative surface finish. The results revealed that, the addition of KGC was beneficial in improving the total thickness of interfacial intermetallic compound (IMC) layer. At higher isothermal ageing of 150 °C and 1000 h, the IMC layer in SAC305-KGC composite solder was towards a planar-type morphology. Moreover, the growth of total interfacial IMC layer and Cu3Sn layer during isothermal ageing was found to be controlled by bulk diffusion and grain-boundary process, respectively. The activation energy possessed by SAC305-KGC composite solder for total interfacial IMC layer and Cu3Sn IMC was 74 kJ/mol and 104 kJ/mol, respectively. Based on a lap shear test, the shear strength of SAC305-KGC composite solder exhibited higher shear strength than non-reinforced SAC305 solder. Meanwhile, the solder joints failure mode after shear testing was a combination of brittle and ductile modes at higher ageing temperature and time for SAC305-KGC composite solder.

Validation of the Critical Strain-Based Methodology for Evaluating the Mechanical Safety of Ball Grid Array Solder Joints in a Launch Random Vibration Environment

2021 ◽  
Author(s):  
Tae-Yong Park ◽  
Hyun-Ung Oh
Keyword(s):  
Fatigue Life ◽  
Random Vibration ◽  
Critical Strain ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Mechanical Design ◽  
Ball Grid Array ◽  
Primary Objective ◽  
Circuit Board ◽  
Analytical Approaches

Abstract To overcome the theoretical limitations of Steinberg's theory for evaluating the mechanical safety of the solder joints of spaceborne electronics in a launch random vibration environment, a critical strain-based methodology was proposed and validated in a previous study. However, for the critical strain-based methodology to be used reliably in the mechanical design of spaceborne electronics, its effectiveness must be validated under various conditions of the package mounting locations and the first eigenfrequencies of a printed circuit board (PCB); achieving this validation is the primary objective of this study. For the experimental validation, PCB specimens with ball grid array packages mounted on various board locations were fabricated and exposed to a random vibration environment to assess the fatigue life of the solder joint. The effectiveness of the critical strain-based methodology was validated through a comparison of the fatigue life of the tested packages and their margin of safety, which was estimated using various analytical approaches.

Sign in / Sign up

Export Citation Format

Share Document