scholarly journals Stress Analysis of Printed Circuit Board with Different Thickness and Composite Materials Under Shock Loading

2020 ◽  
Vol 122 (2) ◽  
pp. 661-674
Author(s):  
Kuan-ting Liu ◽  
Chun-lin Lu ◽  
Nyan-Hwa Tai ◽  
Meng-Kao Yeh
Keyword(s):  
Composite Materials ◽  
Stress Analysis ◽  
Shock Loading ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
Different Thickness

Packaging Challenges of Thin High Bandwidth POP

2019 ◽  
Author(s):  
Fletcher (Cheng-Piao) Tung ◽  
Jensen (Ying-Chou) Tsai ◽  
Yu-Po Wang ◽  
Joe (Chih-Nan) Lin ◽  
Gary (Yue-Long) Fan
Keyword(s):  
Printed Circuit Board ◽  
Lower Cost ◽  
Coefficient Of Thermal Expansion ◽  
Cellular Phone ◽  
Circuit Board ◽  
Printed Circuit ◽  
Fine Pitch ◽  
High Bandwidth ◽  
Application Processor ◽  
Different Thickness

Abstract Components for Smartphone has been the biggest driving force of IC industry for years, and one of the most important IC is application processor (AP). AP needs to work with low power double data rate (LPDDR), the mobile DRAM together for the primary processing of cellular phone and other smart functions. At the beginning, they were packaged separately and then mounted onto printed circuit board (PCB) very close to each other. Nowadays, AP for flagship Smartphone is packaged with a variety of PoP (package on package) structures to shorten the communication distance between AP and LPDDR as well as to save more rooms for battery. High bandwidth package on package (HBW-POP) is the most popular structure among them. As compared to other substrate based PoP, HBW-POP provides the most top side pin count while keeps larger ball pitch for system assembly house to mount LPDDR packaged by fine-pitch ball grid array (FBGA) on top of it. And compared to novel Fan-Out based PoP, HBW-POP has lower cost for AP packaging. In addition, maximum package height of HBW-POP has been shrinking. It is because when LPDDR is mounted onto HBW-POP, the combination is always the tallest chips on the PCB, which determines how slim specific Smartphone can be. HBW-POP consists of 3 parts to encapsulate AP die, and they are top 2-layer substrate, middle molding and bottom 3-layer substrate. Each part has its own coefficient of thermal expansion (CTE) and rigidity, and the warpage performance of HBW-POP is important to align the warpage behavior of LPDDR. The warpage of HBW-POP needs to align with FBGA properly during reflow for good joint, but when HBW-POP becomes thinner, the rigidity of its different parts is changed, which result in different warpage behavior during the reflow. In this paper, we will review the challenges of thin HBW-POP packaging, meanwhile we will explore possible solutions to address each challenge. The study includes the screening of different thickness combination of the 3 parts of HBW-POP, and the optimization of the rigidity and CTE of them. Design of Experiments (DOE) are conducted to find solutions which can meet warpage target, and finally, we present more different tests to prove the reliability of our results.

Interfacial Delamination and Fracture Properties of Potting Compounds and PCB/Epoxy Interfaces Under Flexure Loading After Exposure to Multiple Cure Temperatures

2017 ◽  
Author(s):  
Pradeep Lall ◽  
Kalyan Dornala ◽  
Jeff Suhling ◽  
John Deep
Keyword(s):  
Finite Element ◽  
Shock Loading ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Fracture Properties ◽  
Printed Circuit ◽  
Interfacial Delamination ◽  
Ultimate Elongation ◽  
Point Bend ◽  
Potting Compound

Electronics components operating under extreme thermo-mechanical stresses are often protected with conformal coating and potting encapsulation to isolate the thermal and vibration shock loads. Development of predictive models for high-g shock survivability of electronics requires the measurement of the interface properties of the potting compounds with the printed circuit board materials. There is scarcity of interface fracture properties of porting compounds with printed circuit board materials. Potting and encapsulation resins are commonly two-part systems which when mixed together form a solid, fully cured material, with no by-products. The cured potting materials are prone to interfacial delamination under dynamic shock loading which in turn potentially cause failures in the package interconnects. The study of interfacial fracture resistance in PCB/epoxy potting systems under dynamic shock loading is important in mitigating the risk of system failure in mission critical applications. In this paper three types of epoxy potting compounds were used as an encapsulation on PCB samples. The potting compounds were selected on the basis of their ultimate elongation under quasi-static loading. Potting compound, A is stiffer material with 5% of ultimate elongation before failure. Potting compound, B is a moderately stiff material with 12% ultimate elongation. Finally potting compound C is a softer material with 90% ultimate elongation before failure. The fracture properties and interfacial crack delamination of the PCB/epoxy interface was determined using three-point bend loading with a pre-crack in the epoxy near the interface. The fracture toughness and crack initiation of the three epoxy systems was compared with the cure schedule and temperature. Fracture modeling was performed with crack tip elements in ABAQUS finite element models to determine the crack initiation and interfacial stresses. A comparison of the fracture properties and the performance of epoxy system resistance to delamination was shown through the three-point bend tests. The finite element model results were correlated with the experimental findings.

Characteristics of Radiated Emission from a Printed Circuit Board with a Slit

2012 ◽  
Vol 132 (6) ◽  
pp. 404-410 ◽  
Author(s):  
Kenichi Nakayama ◽  
Kenichi Kagoshima ◽  
Shigeki Takeda
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
Radiated Emission

Confirming the Signal Integrity in Transmission of Digital Signals on Microstrip Straight Circuits via the Eye Diagrams

2014 ◽  
Vol 5 (1) ◽  
pp. 737-741
Author(s):  
Alejandro Dueñas Jiménez ◽  
Francisco Jiménez Hernández
Keyword(s):  
Integrated Circuits ◽  
Printed Circuit Board ◽  
Signal Integrity ◽  
High Volume ◽  
Information Storage ◽  
Circuit Board ◽  
Electromagnetic Simulation ◽  
Electronic Systems ◽  
Digital Signals ◽  
Printed Circuit

Because of the high volume of processing, transmission, and information storage, electronic systems presently requires faster clock speeds tosynchronizethe integrated circuits. Presently the “speeds” on the connections of a printed circuit board (PCB) are in the order of the GHz. At these frequencies the behavior of the interconnects are more like that of a transmission line, and hence distortion, delay, and phase shift- effects caused by phenomena like cross talk, ringing and over shot are present and may be undesirable for the performance of a circuit or system.Some of these phrases were extracted from the chapter eight of book “2-D Electromagnetic Simulation of Passive Microstrip Circuits” from the corresponding author of this paper.

Root Cause Analysis of a Connector Time-Delayed Fracture

2015 ◽  
Author(s):  
Prabjit Singh ◽  
Ying Yu ◽  
Robert E. Davis
Keyword(s):  
Printed Circuit Board ◽  
Ceramic Substrate ◽  
Circuit Board ◽  
Delayed Fracture ◽  
Ceramic Substrates ◽  
Printed Circuit ◽  
Root Cause ◽  
Chip Carrier ◽  
Electrical Connections ◽  
Grain Boundary Grooves

Abstract A land-grid array connector, electrically connecting an array of plated contact pads on a ceramic substrate chip carrier to plated contact pads on a printed circuit board (PCB), failed in a year after assembly due to time-delayed fracture of multiple C-shaped spring connectors. The land-grid-array connectors analyzed had arrays of connectors consisting of gold on nickel plated Be-Cu C-shaped springs in compression that made electrical connections between the pads on the ceramic substrates and the PCBs. Metallography, fractography and surface analyses revealed the root cause of the C-spring connector fracture to be plating solutions trapped in deep grain boundary grooves etched into the C-spring connectors during the pre-plating cleaning operation. The stress necessary for the stress corrosion cracking mechanism was provided by the C-spring connectors, in the land-grid array, being compressed between the ceramic substrate and the printed circuit board.

Application of Lock-in Thermography on PCB for Fault Localization and Validation of Failure Mechanism Due to External Discrete Component Variation

2010 ◽  
Author(s):  
William Ng ◽  
Kevin Weaver ◽  
Zachary Gemmill ◽  
Herve Deslandes ◽  
Rudolf Schlangen
Keyword(s):  
Failure Mechanism ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Hot Spot ◽  
Circuit Board ◽  
Discrete Component ◽  
Printed Circuit ◽  
Thermal Signature ◽  
Lock In

Abstract This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.

Temperature and Humidity Dependent Reliability Analysis of RGB LED Chips

2006 ◽  
Author(s):  
Jun-Xian Fu ◽  
Shukri Souri ◽  
James S. Harris
Keyword(s):  
Reliability Analysis ◽  
Printed Circuit Board ◽  
Light Emitting Diode ◽  
Circuit Board ◽  
Light Emitting ◽  
Printed Circuit ◽  
Root Cause ◽  
Micro Cracks ◽  
Temperature And Humidity

Abstract Temperature and humidity dependent reliability analysis was performed based on a case study involving an indicator printed-circuit board with surface-mounted multiple-die red, green and blue light-emitting diode chips. Reported intermittent failures were investigated and the root cause was attributed to a non-optimized reflow process that resulted in micro-cracks and delaminations within the molding resin of the chips.

Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint

2004 ◽  
Author(s):  
Norman J. Armendariz ◽  
Prawin Paulraj
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Gold Surface ◽  
Circuit Board ◽  
Lead Free ◽  
Processing Temperature ◽  
The European Union ◽  
Printed Circuit ◽  
Higher Temperature ◽  
Tin Silver Copper

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

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