A Solder Joint Reliability Model for the Philips Lumileds LUXEON Rebel LED Carrier Using Physics of Failure Methodology

2013 ◽  
Vol 2013 (1) ◽  
pp. 000887-000892 ◽  
Author(s):  
Rudi Hechfellner ◽  
Michiel Kruger ◽  
Tewe Heemstra ◽  
Greg Caswell ◽  
Nathan Blattau ◽  
...  

Light Emitting Diodes (LEDs) are quickly evolving as the dominant lighting solution for a wide variety of applications. With the elimination of incandescent light bulbs and the toxic limitations of fluorescent bulbs, there has been a dramatic increase in the interest in high-brightness light emitting diodes (HB-LEDs). Getting the light out of the die, with reliable color, while maintaining appropriate thermal control over a long service life is a challenge. These issues must be understood and achieved to meet the needs of unique applications, such as solidstate-lighting, automotive, signage, and medical applications. These applications have requirements for 15–25 years of operation making their reliability of critical importance. The LUXEON Rebel has been accepted as an industry leading LED product, widely used in Mean-Time-Between-Failure (MTBF) sensitive applications. Customers use various mounting platforms, such as FR4 Printed Circuit Board (PCB), FR4 PCB with thermal via's, Aluminum & Copper Metal Core printed Circuit Boards (MCPCB), Super MCPCB, etc. As in other LEDs, when mounting to a platform where a large Coefficient of Thermal Expansion (CTE) exists between the LED & the PCB, Solder fatigue could become an issue that may affect system level lifetime. In this paper we have examined extreme cases and how a solder joint can impact system level reliability. We have modeled the conditions and formed a means to predict system level reliability. We have compared the prediction modeling with empirical tests for validation of the models. It is vital to understand system level reliability factors to build lighting solutions that match the application and customer expectations. It is impractical to test LEDs and other components for 50k hours ~5 years since the device evolution is much faster than that – on average one LED generation every 12–18 month. Hence we need models and prediction methods …..

Author(s):  
M. Baris Dogruoz ◽  
Gokul Shankaran ◽  
Gregory Pitner ◽  
Manoj Nagulapally

A printed circuit board (PCB) consists of consecutive layers of dielectric material and current carrying traces and vias. Conducting system level simulations of PCB’s with detailed trace and via geometries is computationally very expensive. In the present study, the effects of the trace and via geometry in the physical model are taken into account by importing the corresponding ECAD data with which locally varying anisotrpoic thermal conductivity on the PCB is determined accordingly. Moreover, the effects of Joule heating in the current carrying traces are included by using a number of planar heat sources representing individual metal trace layers. The powermap on each of these layers is determined by solving the relevant electric field equations where the temperature dependency of the electrical field is also taken into account. The results are presented on a sample PCB and comparisons are made with the previous studies and conventional models. It is demonstrated that temperature values differ substantially depending on the method of Joule heating treatment used.


Author(s):  
Wenjun Liu ◽  
Min-Young Lee ◽  
Younes Shabany ◽  
Mehdi Asheghi

This paper presents a simple yet novel analytical approach to model the heat conduction in a Printed Circuit Board (PCB) by taking advantage of the large thermal conductivity contrast between the copper and glass-epoxy layers. The model provides a compact expression for the effective thermal resistance of a PCB and captures an approximate 2-dimensional temperature distribution within the PCB copper layer using simple one-dimensional fin equations in successive copper-glass epoxy layers. The results for effective thermal resistance and temperature distributions in copper layers agree within ±10% of those predicted using finite element (FEM) simulations. The present approach can significantly improve the system level thermal modeling and design of single and multi-component PCBs.


Author(s):  
Jun-Xian Fu ◽  
Shukri Souri ◽  
James S. Harris

Abstract Temperature and humidity dependent reliability analysis was performed based on a case study involving an indicator printed-circuit board with surface-mounted multiple-die red, green and blue light-emitting diode chips. Reported intermittent failures were investigated and the root cause was attributed to a non-optimized reflow process that resulted in micro-cracks and delaminations within the molding resin of the chips.


Author(s):  
Norman J. Armendariz ◽  
Prawin Paulraj

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.


Author(s):  
P. Singh ◽  
G.T. Galyon ◽  
J. Obrzut ◽  
W.A. Alpaugh

Abstract A time delayed dielectric breakdown in printed circuit boards, operating at temperatures below the epoxy resin insulation thermo-electrical limits, is reported. The safe temperature-voltage operating regime was estimated and related to the glass-rubber transition (To) of printed circuit board dielectric. The TG was measured using DSC and compared with that determined from electrical conductivity of the laminate in the glassy and rubbery state. A failure model was developed and fitted to the experimental data matching a localized thermal degradation of the dielectric and time dependency. The model is based on localized heating of an insulation resistance defect that under certain voltage bias can exceed the TG, thus, initiating thermal degradation of the resin. The model agrees well with the experimental data and indicates that the failure rate and truncation time beyond which the probability of failure becomes insignificant, decreases with increasing glass-rubber transition temperature.


2021 ◽  
Vol 11 (6) ◽  
pp. 2808
Author(s):  
Leandro H. de S. Silva ◽  
Agostinho A. F. Júnior ◽  
George O. A. Azevedo ◽  
Sergio C. Oliveira ◽  
Bruno J. T. Fernandes

The technological growth of the last decades has brought many improvements in daily life, but also concerns on how to deal with electronic waste. Electrical and electronic equipment waste is the fastest-growing rate in the industrialized world. One of the elements of electronic equipment is the printed circuit board (PCB) and almost every electronic equipment has a PCB inside it. While waste PCB (WPCB) recycling may result in the recovery of potentially precious materials and the reuse of some components, it is a challenging task because its composition diversity requires a cautious pre-processing stage to achieve optimal recycling outcomes. Our research focused on proposing a method to evaluate the economic feasibility of recycling integrated circuits (ICs) from WPCB. The proposed method can help decide whether to dismantle a separate WPCB before the physical or mechanical recycling process and consists of estimating the IC area from a WPCB, calculating the IC’s weight using surface density, and estimating how much metal can be recovered by recycling those ICs. To estimate the IC area in a WPCB, we used a state-of-the-art object detection deep learning model (YOLO) and the PCB DSLR image dataset to detect the WPCB’s ICs. Regarding IC detection, the best result was obtained with the partitioned analysis of each image through a sliding window, thus creating new images of smaller dimensions, reaching 86.77% mAP. As a final result, we estimate that the Deep PCB Dataset has a total of 1079.18 g of ICs, from which it would be possible to recover at least 909.94 g of metals and silicon elements from all WPCBs’ ICs. Since there is a high variability in the compositions of WPCBs, it is possible to calculate the gross income for each WPCB and use it as a decision criterion for the type of pre-processing.


Sign in / Sign up

Export Citation Format

Share Document