Cu/SnAg Double Bump Flip Chip Assembly as an Alternative of Solder Flip Chip on Organic Substrates for Fine Pitch Applications

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.

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Sub process challenges in ultra fine pitch stencil printing of type‐6 and type‐7 Pb‐free solder pastes for flip chip assembly applications

Soldering & Surface Mount Technology ◽

10.1108/09540910510579212 ◽

2005 ◽

Vol 17 (1) ◽

pp. 24-32 ◽

Cited By ~ 23

Author(s):

G.J. Jackson ◽

M.W. Hendriksen ◽

R.W. Kay ◽

M. Desmulliez ◽

R.K. Durairaj ◽

...

Keyword(s):

Flip Chip ◽

Stencil Printing ◽

Fine Pitch ◽

Solder Pastes ◽

Flip Chip Assembly ◽

Free Solder

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Corrections to "Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process"

IEEE Transactions on Components and Packaging Technologies ◽

10.1109/tcapt.2007.895649 ◽

2007 ◽

Vol 30 (2) ◽

pp. 359-359

Author(s):

Robert W. Kay ◽

Stoyan Stoyanov ◽

Greg P. Glinski ◽

Chris Bailey ◽

Marc P. Y. Desmulliez

Keyword(s):

Low Temperature ◽

Flip Chip ◽

Low Cost ◽

Assembly Process ◽

Stencil Printing ◽

Fine Pitch ◽

Flip Chip Assembly

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Lead-Free Flip Chip Assembly

Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology ◽

10.1115/imece2002-39251 ◽

2002 ◽

Cited By ~ 1

Author(s):

Sunil Gopakumar ◽

Vinodh Poyyapakkam ◽

Dan Blass ◽

Peter Borgesen ◽

K. Srihari

Keyword(s):

Flip Chip ◽

Lead Free ◽

Organic Substrates ◽

Flip Chips ◽

Solder Volume ◽

Two Factors ◽

Incomplete Wetting ◽

Flip Chip Assembly

It is well established that Pb free alloys tend to solder less readily than Sn/Pb. It is not clear that this is always a major problem, but two factors combine to make it more of a concern for flip chip than for other applications. Not surprisingly, wetting and spreading appears to become less effective as the solder volume is reduced and a larger fraction of it is near the surface. At the same time assembly yields tend to become more sensitive to this. The present paper addresses the assembly of flip chips with Sn/Ag/Cu bumps onto Ni/Au and OSP coated copper pads on organic substrates. Soldering defects observed included incomplete wetting and collapse, as well as poor self centering. The sensitivity to fluxes, reflow profiles, and substrate pads were investigated and potential consequences for assembly yields calculated numerically.

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Influence of the Property of the Build-Up Package on Warpage at Flip Chip Assembly Process

2003 International Electronic Packaging Technical Conference and Exhibition, Volume 2 ◽

10.1115/ipack2003-35262 ◽

2003 ◽

Author(s):

Yukihiko Toyoda ◽

Yoichiro Kawamura ◽

Hiroyoshi Hiei ◽

Qiang Yu ◽

Tadahiro Shibutani ◽

...

Keyword(s):

Flip Chip ◽

Electronic Device ◽

New Product ◽

High Density ◽

Simulation Technique ◽

Assembly Process ◽

Reliability Problem ◽

Fine Pitch ◽

Flip Chip Assembly ◽

Single Material

High density and integrated packaging of electronic device requires fine pitch. This packaging causes reliability problem in electronic device. One of them, warpage of the package occurred at chip assembly process may affect reliability. Therefore, if the simulation at the time of a chip assembly process is possible, it will be able to evaluate warpage in advance. It is very effective for development of a new product. Then, in this paper, the build-up package is regarded as a single material and the simulation technique of accuracy warpage at the time of chip assembly is reported. Next it is investigated the simulation technique for package warpage at the chip assembly process. Finnaly, it analyzed about the properties which affect warpage.

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