Investigation of the Initial Silicon-on-Sapphire Layer Formed by CVD Techniques

2019 ◽  
Vol 53 (15) ◽  
pp. 2016-2023
Author(s):  
S. D. Fedotov ◽  
E. M. Sokolov ◽  
V. N. Statsenko ◽  
A. V. Romashkin ◽  
S. P. Timoshenkov
Keyword(s):  
Initial Silicon

CALCULATION OF STAGES OF THE TECHNOLOGICAL PROCESS OF MANUFACTURE OF PPD DETECTORS USING COMPUTER MATHEMATICAL MODELING AND PRODUCTION OF ALPHA RADIOMETER ON THEIR BASIS

2020 ◽  
Vol 7 (2) ◽  
pp. 21-28
Author(s):  
SALI RADZHAPOV ◽  
◽  
RUSTAM RAKHIMOV ◽  
BEGJAN RADZHAPOV ◽  
MARS ZUFAROV
Keyword(s):  
Mathematical Modeling ◽  
Technological Process ◽  
Block Diagram ◽  
Large Diameter ◽  
Silicon Detector ◽  
Digital Processing ◽  
Main Element ◽  
Alpha Radiation ◽  
Initial Silicon ◽  
Natural Isotopes

The article describes the developed radiometer for Express measurement of alpha radiation of radioactive elements based on a large-diameter silicon detector. The main element of the PPD detector is made using computer mathematical modeling of all stages of the technological process of manufacturing detectors, taking into account at each stage the degree of influence of the properties of the initial silicon on the electrophysical and radiometric characteristics of the detector. Detectors are manufactured for certain types of devices. The developed radiometer is designed to measure alpha radiation of natural isotopes (238U, 234U, 232Th, 226Ra, 222Rn, 218Po, 214Bi, etc.) in various environments. It also shows the principle of operation of the device, provides a block diagram of the measuring complex, describes the electronic components of the radiometer, as well as the block diagram. Signal transformations (spectrum transfer, filtering, accumulation) are implemented programmatically on the basis of a digital processing module. The device can detect the presence of specific elements in various environments, as well as protect people from the harmful effects of adverse radiation and can be used both in the field and stationary.

The Removal of Impurity Silicon from Aluminum Melt by the Addition of K2TiF6

2017 ◽  
Vol 748 ◽  
pp. 192-196 ◽  
Author(s):  
Guo Liang Zhu ◽  
Rui Wang ◽  
Wei Wang ◽  
Da Shu ◽  
An Ping Dong ◽  
...  
Keyword(s):  
Removal Efficiency ◽  
Silicon Concentration ◽  
Aluminum Melt ◽  
Purification Efficiency ◽  
Initial Silicon ◽  
Novel Method ◽  
Holding Temperature

A novel method to remove impurity silicon from aluminum melt by the addition of K2TiF6 was studied. The mechanism for silicon removal is the formation and sedimentation of Ti(Al1-x,Six)3 phase and the removal efficiency is mostly decided by the solubility of silicon in TiAl3 phase, which increases with the increasing of the initial silicon concentration in aluminum melt. The effect of holding temperature on the impurity Si purification efficiency was investigated and the result indicated that the effect of holding temperature is very finite.

Rietveld Studies on Silicon Substituted Hydroxyapatite

2006 ◽  
Vol 309-311 ◽  
pp. 113-116 ◽  
Author(s):  
Shuo Zou ◽  
Jie Huang ◽  
Serena Best ◽  
William Bonfield
Keyword(s):  
Silicon Content ◽  
Sintering Temperature ◽  
Silicon Concentration ◽  
Crystallographic Structure ◽  
X Ray Diffraction ◽  
Phase Purity ◽  
X Ray ◽  
Similar Dependence ◽  
Initial Silicon ◽  
Distortion Index

Silicon-substituted hydroxyapatite (SiHA) attracts particular interest due its enhanced bioactivity compared with pure hydroxyapatite. In this study we seek to clarify the effects on the lattice parameters of both composition and sintering temperature in experimentally-produced HA and 0.8wt% SiHA, 1.5wt% SiHA and 2.0wt% SiHA sintered at 800oC and 1200oC. X ray diffraction was used to determine the phase purity and crystallographic structure. We found that while the c parameter increased with increasing silicon concentration, the a parameter decreased with initial silicon incorporation then recovered with further increases in silicon incorporation. The calcium (2) channel expanded with silicon incorporation while tetrahedron distortion index (TDI) and the radius of the P channel showed a similar dependence on silicon content as the a parameter.

Effects of Technical Parameters on Initial Silicon Melting in Round Cold Crucible Continuous Casting

2012 ◽  
Vol 472-475 ◽  
pp. 740-743
Author(s):  
Rui Run Chen ◽  
Feng Huang ◽  
Jing Jie Guo ◽  
Hong Sheng Ding ◽  
Yan Qing Su ◽  
...  
Keyword(s):  
Theoretical Analysis ◽  
Continuous Casting ◽  
Cold Crucible ◽  
Technical Parameters ◽  
Initial Melting ◽  
Initial Silicon

The effects of technical parameters on initial silicon melting in cold crucible continuous casting were studied. These parameters include the materials, the shape and the position of the base, the mass of the silicon that set on the top of the base. Through experimental and theoretical analysis, the optimized parameters were finally given: the base graphite with obconical shaped should be put at the level of the second turn of the coil, and the initial silicon with 10g should be put on the base. The mechanism of these parameters affecting on the initial melting are discussed and revealed.

Fabrication of Silicon Nanowires by Electron Beam Lithography and Thermal Oxidation Size Reduction Method

2013 ◽  
Vol 832 ◽  
pp. 415-418 ◽  
Author(s):  
Mohammad Nuzaihan Md Nor ◽  
Uda Hashim ◽  
Taib Nazwa ◽  
Tijjani Adam
Keyword(s):  
Electron Beam ◽  
Thermal Oxidation ◽  
Silicon Nanowires ◽  
Electron Beam Lithography ◽  
Reduction Method ◽  
Size Reduction ◽  
Simple Method ◽  
Force Microscopy ◽  
Initial Silicon ◽  
20 Nm

A simple method for the fabrication of silicon nanowires using Electron Beam Lithography (EBL) combined with thermal oxidation size reduction method is presented. EBL is used to define the initial silicon nanowires of dimensions approximately 100 nm. Size-reduction method is employed for reaching true nanoscale of dimensions approximately 20 nm. Dry oxidation of silicon is well investigated process for self-limited size-reduction of silicon nanowires. In this paper, successful size reduction of silicon nanowires is presented and surface topography characterizations using Atomic Force Microscopy (AFM) are reported.

scholarly journals An integral feature of porous silicon and its classification

2021 ◽  
Vol 23 (3) ◽  
pp. 440-444
Author(s):  
Andrey M. Khort ◽  
Anatoliy G. Yakovenko ◽  
Yury V. Syrov
Keyword(s):  
Porous Silicon ◽  
Pore Size ◽  
Internal Surface ◽  
Practical Implementation ◽  
Integral Parameter ◽  
Detailed Classification ◽  
Initial Silicon ◽  
Almost All ◽  
Integral Feature

Porous silicon is currently one of the most studied materials which is used both in the areas traditional for silicon, such as electronics and optoelectronics, and in completely unconventional ones, such as catalysis, energetics, biology, and medicine. The multiple possibilities of the material are revealed due to the fact that its structure can be radically different depending on the properties of the initial silicon and the methods of obtaining porous phases. The use of any material inevitably leads to the need to classify its various forms. The purpose of the article was to find the most significant parameter that can be used as the basis for the classification of porous silicon.Historically, the terminology defined by the IUPAC pore size classification has been used to classify porous silicon. Due to the authority of IUPAC, many researchers have considered this terminology to be the most successful and important, and the radial pore size has often been regarded as a main parameter containing the most important properties of porous silicon. Meanwhile, the unique properties and practical application of porous silicon are based on its developed inner surface. The method of nitrogen porosimetry, which is simple in its practical implementation, is often used in scientific literature to determine this value.The most suitable integral parameter for the classification of porous silicon, regardless of its structure and morphology, is the total specific internal surface (cm-1) that can be relatively easily established experimentally and is of fundamental importance for almost all applications of porous silicon. The use of this value does not exclude the use of other parameters for a more detailed classification

scholarly journals Reliability Express Control of the Gate Dielectric of Semiconductor Devices

2018 ◽  
Vol 9 (4) ◽  
pp. 308-313
Author(s):  
V. A. Solodukha ◽  
G. G. Chigir ◽  
V. A. Pilipenko ◽  
V. A. Filipenya ◽  
V. A. Gorushko
Keyword(s):  
Thermal Treatment ◽  
Integrated Circuits ◽  
Gate Dielectric ◽  
Semiconductor Devices ◽  
Silicon Wafers ◽  
Express Method ◽  
Running Time ◽  
Reliability Indicators ◽  
Initial Silicon ◽  
Free Running

The key element determining stability of the semiconductor devices is a gate dielectric. As its thickness reduces in the process of scaling the combined volume of factors determining its electrophysical properties increases. The purpose of this paper is development of the control express method of the error-free running time of the gate dielectric and study the influence of the rapid thermal treatment of the initial silicon wafers and gate dielectric on its reliability.The paper proposes a model for evaluation of the reliability indicators of the gate dielectrics as per the trial results of the test MDS-structures by means of applying of the ramp-increasing voltage on the gate up to the moment of the structure breakdown at various velocities of the voltage sweep with measurement of the IV-parameters. The proposed model makes it possible to realize the express method of the reliability evaluation of the thin dielectrics right in the production process of the integrated circuits.On the basis of this method study of the influence of the rapid thermal treatment of the initial silicon wafers of the KEF 4.5, KDB 12 wafers and formed on them by means of the pyrogenic oxidation of the gate dielectric for the error-free running time were performed. It is shown, that rapid thermal treatment of the initial silicon wafers with their subsequent oxidation results in increase of the error-free running time of the gate dielectric on average from 12.9 to 15.9 years (1.23 times greater). Thermal treatment of the initial silicon wafers and gate dielectric makes it possible to expand the error-free running time up to 25.2 years, i.e.1.89 times more, than in the standard process of the pyrogenic oxidation and 1.5 times more, than under application of the rapid thermal treatment of the initial silicon wafers only.

A systematic study of silicon nanowires array fabricated through metal-assisted chemical etching

2020 ◽  
Vol 92 (3) ◽  
pp. 30402
Author(s):  
Shiying Zhang ◽  
Zhenhua Li ◽  
Qingjun Xu
Keyword(s):  
Electron Microscopy ◽  
Silicon Nanowires ◽  
Chemical Etching ◽  
Optimal Solution ◽  
Solution Concentration ◽  
Etching Time ◽  
Si Nanowires ◽  
Selected Area Electron Diffraction ◽  
Initial Silicon ◽  
Metal Assisted Chemical Etching

Aligned and uniform silicon nanowires (SiNWs) arrays were fabricated with good controllability and reproducibility by metal-assisted chemical etching in aqueous AgNO3/HF etching solutions in atmosphere. The SiNWs formed on silicon were characterized by scanning electron microscopy (SEM), energy-dispersive X-ray (EDX), high-resolution transmission electron microscopy (HRTEM) and selected-area electron diffraction (SAED). The results show that the as-prepared SiNWs are perfectly single crystals and the axial orientation of the Si nanowires is identified to be parallel to the [111] direction, which is identical to the initial silicon wafer. In addition, a series of experiments were conducted to study the effects of etching conditions such as solution concentration, etching time, and etching temperature on SiNWs. And the optimal solution concentrations for SiNWs have been identified. The formation mechanism of silicon nanowires and silver dendrites were also discussed.

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