RECENT ADVANCES AND DESIGN TRENDS IN CMOS RADIO FREQUENCY INTEGRATED CIRCUITS

2005 ◽  
Vol 15 (02) ◽  
pp. 377-428
Author(s):  
DAVID J. ALLSTOT ◽  
SANKARAN ANIRUDDHAN ◽  
MIN CHU ◽  
JEYANANDH PARAMESH ◽  
SUDIP SHEKHAR
Keyword(s):  
Integrated Circuits ◽  
Phase Noise ◽  
Noise Figure ◽  
Building Blocks ◽  
Intermediate Frequency ◽  
Direct Conversion ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Common Source ◽  
Lower Phase

Several state-of-the-art wireless receiver architectures are presented including the traditional super-heterodyne, the image-reject heterodyne, the direct-conversion, and the very-low intermediate frequency (VLIF). The case studies are followed by a detailed view of receiver building blocks: low-noise amplifiers (LNA), mixers, and voltage-controlled oscillators (VCO). Two popular topologies currently exist for LNAs: the common-gate configuration, which offers low power consumption with superior stability, robustness and linearity performance, and its common-source counterpart, which provides comparatively higher gain and lower noise figure. Aside from the traditional passive and active Gilbert mixers, the even-harmonic and masking-quadrature mixers are developed to combat second-order non-linearity and improve image-rejection, respectively. For quadrature carrier generation, the degeneration-injected QVCO is superior to the cascode-injected QVCO both in terms of phase noise and tuning range. The Colpitts QVCO is attractive as a low-noise alternative as it does not disturb the output voltage as much as its traditional LC counterpart and thus offers lower phase noise.

GaN-based amplifiers for wideband applications

2010 ◽  
Vol 2 (1) ◽  
pp. 135-141 ◽  
Author(s):  
Patrick Schuh ◽  
Hardy Sledzik ◽  
Rolf Reber ◽  
Kristina Widmer ◽  
Martin Oppermann ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Power Amplifiers ◽  
Building Blocks ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Electronic Warfare ◽  
Monolithically Integrated ◽  
Gan Hemt ◽  
System Approaches ◽  
Lower Frequencies

Different wideband amplifiers, hybrid designs at lower frequencies, and monolithically integrated circuits (MMIC) at higher frequencies were designed, fabricated, and measured. These amplifiers are all based on AlGaN/GaN HEMT technology. The future applications for these types of amplifiers are mainly electronic warfare (EW) applications. Novel communication jammers and especially active electronically scanned array EW systems have a high demand for wideband high power amplifiers. The second application also needs high robust low noise amplifiers for its receive path. Output power levels of 38 W for hybrid amplifiers at lower frequencies up to 6 GHz and 15 W for the MMIC power amplifiers at higher frequencies are measured. With these building blocks, novel EW system approaches can be investigated.

6–12 GHz double-balanced image-reject mixer MMIC in 0.25 µm AlGaN/GaN technology

2015 ◽  
Vol 7 (3-4) ◽  
pp. 307-315 ◽  
Author(s):  
Marc van Heijningen ◽  
Jeroen A. Hoogland ◽  
Peter de Hek ◽  
Frank E. van Vliet
Keyword(s):  
Integrated Circuits ◽  
Intermediate Frequency ◽  
Local Oscillator ◽  
Input Power ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Conversion Loss ◽  
Front End ◽  
Signal Amplifier ◽  
Measurement Results

The front-end circuitry of transceiver modules is slowly being updated from GaAs-based monolithic microwave integrated circuits (MMICs) to Gallium-Nitride (GaN). Especially GaN power amplifiers and T/R switches, but also low-noise amplifiers (LNAs), offer significant performance improvement over GaAs components. Therefore it is interesting to also explore the possible advantages of a GaN mixer to enable a fully GaN-based front-end. In this paper, the design-experiment and measurement results of a double-balanced image-reject mixer MMIC in 0.25 μm AlGaN/GaN technology are presented. First an introduction is given on the selection and dimensioning of the mixer core, in relation to the linearity and conversion loss. At the intermediate frequency (IF)-side of the mixer, an active balun has been used to compensate partly for the loss of the mixer. An on-chip local-oscillator (LO) signal amplifier has been incorporated so that the mixer can function with 0 dBm LO input power. After the discussion of the circuit design the measurement results are presented. The performance of the mixer core and passive elements has been demonstrated by measurements on a test-structure. The mixer MMIC measured conversion loss is <8 dB from 6 to 12 GHz, at 1 GHz IF and 0 dBm LO power. The measured image rejection is better than 30 dB.

scholarly journals A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 785
Author(s):  
Juan L. Castagnola ◽  
Fortunato C. Dualibe ◽  
Agustín M. Laprovitta ◽  
Hugo García-Vázquez
Keyword(s):  
Integrated Circuits ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Optimization Approach ◽  
Scattering Parameters ◽  
Rf Integrated Circuits ◽  
Design And Optimization ◽  
Noise Amplifier

This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.

Ultra-low Residue Flux Applications in RF Front-End Packages

2020 ◽  
Vol 2020 (1) ◽  
pp. 000125-000130
Author(s):  
Leo Hu ◽  
Sze Pei Lim
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Reflow Process ◽  
Reliability Study ◽  
Rf Switches ◽  
Front End ◽  
Rf Front End ◽  
Package Reliability

Abstract With the leap into the 5G era, the demand for improvements in the performance of mobile phones is on the rise. This is also true for the quantity of radio frequency (RF) front-end integrated circuits (ICs), especially for RF switches and low noise amplifiers (LNA). It is well-known that improvements in performance depend on the combination of new design, package technology, and choice of materials. Ultra-low residue (ULR) flux is an innovative, truly no-clean, flip-chip bonding material. By using ULR flux, the typical water-wash cleaning process can be removed and, in some instances, package reliability can be improved as well. This simplified assembly process will help to reduce total packaging costs. This paper will discuss the application of ULR fluxes on land grid arrays (LGAs) and quad-flat no-leads/dual-flat no-leads (QFN/DFN) packages for RF front-end ICs, as well as the reflow process. The solder joint strength and reliability study will be shared as well.

Inductive Feedback Technique for Design of High Gain 0.18μm CMOS LNA for 5G Applications

2021 ◽  
pp. 2150236
Author(s):  
Anjana Jyothi Banu ◽  
G. Kavya ◽  
D. Jahnavi
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Common Source ◽  
Matching Network ◽  
Input Matching ◽  
Cmos Lna ◽  
Noise Amplifier

A 26[Formula: see text]GHz low-noise amplifier (LNA) designed for 5G applications using 0.18[Formula: see text][Formula: see text]m CMOS technology is proposed in this paper. The circuit includes a common-source in the first stage to suppress the noise in the amplifier. The successive stage has a Cascode topology along with an inductive feedback to improve the power gain. The input matching network is designed to achieve the input reflection coefficient less than [Formula: see text]7dB at the intended frequency. The matching network at the output is designed using inductor–capacitor (LC) components connected in parallel to attain the output reflection coefficient of [Formula: see text]10[Formula: see text]dB. Due to the inductor added in feedback at the second stage. The [Formula: see text] obtained is 18.208[Formula: see text]dB at 26[Formula: see text]GHz with a noise figure (NF) of 2.8[Formula: see text]dB. The power supply given to the LNA is 1.8[Formula: see text]V. The simulation and layout of the presented circuit are performed using Cadence Virtuoso software.

Passive Components for RF-ICs

2012 ◽  
pp. 189-214
Author(s):  
Gianluca Cornetta ◽  
David J. Santos ◽  
José Manuel Vázquez
Keyword(s):  
Integrated Circuits ◽  
Quality Factor ◽  
Silicon Substrate ◽  
Supply Voltage ◽  
Magnetic Behavior ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Fully Integrated ◽  
Core Elements ◽  
Low Supply Voltage

The modern wireless communication industry is demanding transceivers with a high integration level operating in the gigahertz frequency range. This, in turn, has prompted intense research in the area of monolithic passive devices. Modern fabrication processes now provide the capability to integrate onto a silicon substrate inductors and capacitors, enabling a broad range of new applications. Inductors and capacitors are the core elements of many circuits, including low-noise amplifiers, power amplifiers, baluns, mixers, and oscillators, as well as fully-integrated matching networks. While the behavior and the modeling of integrated capacitors are well understood, the design of an integrated inductor is still a challenging task since its magnetic behavior is hard to predict accurately. As the operating frequency approaches the gigahertz range, device nonlinearities, coupling effects, and skin effect dominate, making difficult the design of critical parameters such as the self-resonant frequency, the quality factor, and self and mutual inductances. However, despite the parasitic effects and the low quality-factor, integrated inductors still allow for the implementation of integrated circuits with improved performances under low supply voltage. In this chapter, the authors review the technology behind monolithic capacitors and inductors on silicon substrate for high-frequency applications, with major emphasis on physical implementation and modeling.

scholarly journals Design of a 40 GHz low noise amplifier using multigate technique for cascode devices

2020 ◽  
Vol 105 (3) ◽  
pp. 347-357
Author(s):  
Rana Azhar Shaheen ◽  
Timo Rahkonen ◽  
Aarno Pärssinen
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Common Source ◽  
Active Devices ◽  
Trade Offs ◽  
Layout Technique ◽  
Noise Amplifier ◽  
Gate Resistance ◽  
Parasitic Components

Abstract Increased parasitic components in silicon-based nanometer (nm) scale active devices have various performance trade-offs between optimizing the key parameters, for example, maximum frequency of oscillation ($$f_{max}$$ f max , gate resistance and capacitance, etc. A common-source cascode device is commonly used in amplifier designs at RF/millimeter-wave (mmWave) frequencies. In addition to intrinsic parasitic components, extrinsic components due to wiring and layout effects, are also critical for performance and accurate modelling of the devices. In this work, a comparison of two different layout techniques for cascode devices is presented to optimize the extrinsic parasitic elements, such as gate resistance. A multi-gate or multi-port layout technique is proposed for optimizing the gate resistance ($$r_g$$ r g ). Extracted values from measurement results show reduction of 10% in $$r_{g}$$ r g of multi-gate layout technique compared to a conventional gate-above-device layout for cascode devices. However, conventional layout exhibits smaller gate-to-source and gate-to-drain capacitances which leads to better performance in terms of speed, i.e. $$f_{max}$$ f max . An LNA is designed at 40 GHz frequency using proposed multi-gate cascode device. LNA achieves a measured peak gain of 10.2 dB and noise figure of 4.2 dB at 40 GHz. All the structures are designed and fabricated using 45 nm CMOS silicon on insulator (SOI) technology.

scholarly journals Technologies, Design, and Applications of Low-Noise Amplifiers at Millimetre-Wave: State-of-the-Art and Perspectives

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1222 ◽  
Author(s):  
Longhi ◽  
Pace ◽  
Colangeli ◽  
Ciccognani ◽  
Limiti
Keyword(s):  
Integrated Circuit ◽  
Noise Figure ◽  
State Of The Art ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Wave State ◽  
Millimetre Wave ◽  
Monolithic Microwave Integrated Circuit ◽  
V Band ◽  
And Performance

An overview of applicable technologies and design solutions for monolithic microwave integrated circuit (MMIC) low-noise amplifiers (LNAs) operating at millimeter-wave are provided in this paper. The review starts with a brief description of the targeted applications and corresponding systems. Advanced technologies are presented highlighting potentials and drawbacks related to the considered possibilities. Design techniques, applicable to different requirements, are presented and analyzed. An LNA operating at V-band (59–66 GHz) is designed and tested following the presented guidelines, demonstrating state-of-the-art results in terms of noise figure (average NF < 2 dB). A state-of-the-art table, reporting recent results available in open literature on this topic, is provided and examined, focusing on room temperature operation and performance in cryogenic environment. Finally, trends versus frequency and perspectives are outlined.

Design Analysis of Inductorless Active Loaded Low Power UWB LNA Using Noise Cancellation Technique

Frequenz ◽  
2020 ◽  
Vol 74 (3-4) ◽  
pp. 137-144 ◽  
Author(s):  
Dheeraj Kalra ◽  
Manish Kumar ◽  
Aasheesh Shukla ◽  
Laxman Singh ◽  
Zainul Abdin Jaffery
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Broad Band ◽  
Wide Band ◽  
Cmos Technology ◽  
Noise Cancellation ◽  
Low Noise ◽  
Design Analysis ◽  
Common Source ◽  
Power Gain

AbstractThis paper includes a design analysis of an inductorless low-power (LP) low-noise amplifier (LNA) with active load for Ultra Wide Band (UWB) applications. The proposed LNA consists of two parallel paths, one is the common source (CS) path and second is the CG path. The CG path has the edge advantage of improving overall Noise figure (NF) due to wide band impedance matching in UWB, while the CS path provides high power gain. A method for noise cancellation is adopted, to reduce the noise of CS path with the help of CG path. The proposed LNA successfully simulated in 90 nm CMOS technology. The results of proposed work indicate optimization at frequency 5.70 GHz with 3 dB bandwidth of 4.3 GHz–8.9 GHz. All simulations have been done for a range of frequency 03 GHz–13 GHz in Cadence virtuoso software. The results quoted 1.15 dB NF, −18.12 dB S11, 13.7 dB S21, maximum operating power gain (GP) 11.756 dB at frequency 5.7 GHz and available power gain (GA) is 10.17 dB at frequency 8.61 GHz, with 0.6 V, 0.92 mW broad band LNA.

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