A CMOS low-noise active mixer with enhanced linearity and isolation by exploiting capacitive neutralization technique

2019 ◽  
Vol 33 (18) ◽  
pp. 1950204 ◽  
Author(s):  
Benqing Guo ◽  
Huifen Wang ◽  
Jun Chen ◽  
Mohammad Mehdi Deilamsalehi
Keyword(s):  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Frequency Range ◽  
Input Stage ◽  
Active Mixer ◽  
Input Matching ◽  
Down Conversion

In this paper, a broadband complementary metal–oxide–semiconductor (CMOS) active down-conversion mixer is presented. Specifically, a capacitor cross-coupled (CCC) transconductor serves as the input stage to reduce noise figure of the mixer while providing wideband input matching. Moreover, a capacitive neutralization technique is used to compensate the source-drain parasitic of input stage and boost loop gain of the transconductor, resulting in improved isolation and linearity. The current-reuse technique applied to the developed transconductor by stacked nMOS/pMOS architecture efficiently saves power consumption of the circuit. Implemented in the TSMC 28-nm CMOS process, post-simulations show that the proposed mixer provides a maximal conversion gain of 11.4 dB and an NF of 3.9–4.7 dB across RF input frequency range of 2–9.6 GHz. The average IIP3 of 5 dBm are obtained while the mixer core consumes 6.2 mW from a 1 V supply.

A FULLY INTEGRATED MULTIBAND CMOS 0.35 μM LNA FOR IEEE802.16 STANDARD

2013 ◽  
Vol 22 (02) ◽  
pp. 1250088 ◽  
Author(s):  
MERIAM BEN AMOR ◽  
MOURAD LOULOU ◽  
SEBASTIEN QUINTANEL ◽  
DANIEL PASQUET
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Cmos Process ◽  
Frequency Range ◽  
Fully Integrated ◽  
Input Matching ◽  
Noise Amplifier ◽  
Chebyshev Filter

In this paper we present the design of a fully integrated low noise amplifier for WiMAX standard with AMS 0.35 μm CMOS process. This LNA is designed to cover the frequency range for licensed and unlicensed bands of the WiMAX 2.3–5.9 GHz. The proposed amplifier achieves a wide band input and output matching with S11 and S22 lower than -10 dB, a flat gain of 12 dB and a noise figure around 3.5 dB for the entire band and from the upper to the higher frequencies. The presented wide band LNA employs a Chebyshev filter for input matching and an inductive shunt feedback for output matching with a bias current of 15 mA and a supply voltage of 2.5 V.

scholarly journals Design and Performance Investigation of a New Distributed Amplifier Architecture for 40 and 100 Gb/s Optical Receivers

2015 ◽  
Vol 14 (5) ◽  
pp. 5661-5686
Author(s):  
Essra E. Al-Bayati ◽  
R. S. Fyath
Keyword(s):  
Communication Systems ◽  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Noise ◽  
Ultra Wideband ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Optical Receivers ◽  
Distributed Amplifier ◽  
Design Scheme

The design of distributed amplifiers (DAs) is one of the challenging aspects in emerging ultra high bit rate optical communication systems. This is especially important when implementation in submicron silicon complementary metal oxide semiconductor (CMOS) process is considered. This work presents a novel design scheme for DAs suitable for frontend amplification in 40 and 100 Gb/s optical receivers. The goal is to achieve high flat gain and low noise figure (NF) over the ultra wideband operating bandwidth (BW). The design scheme combines shifted second tire (SST) matrix configuration with cascode amplification cell configuration and uses m-derived technique. Performance investigation of the proposed DA architecture is carried out and the results are compared with that of other DA architectures reported in the literature. The investigation covers the gain and NF spectra when the DAs are implemented in 180, 130, 90, 65 and 45 CMOS standards.The simulation results reveal that the proposed DA architecture offers the highest gain with highest degree of flatness and low NF when compared with other DA configurations. Gain-BW products of 42772 and 21137 GHz are achieved when the amplifier is designed for 40 and 100 Gb/s operation, respectively, using 45 nm CMOS standard. Thesimulation is performed using AWR Microwave Office (version 10).

An inductorless active mixer using stacked nMOS/pMOS configuration and LO shaping technique

2018 ◽  
Vol 32 (11) ◽  
pp. 1850129 ◽  
Author(s):  
Benqing Guo ◽  
Jun Chen ◽  
Xuebing Wang ◽  
Hongpeng Chen
Keyword(s):  
Noise Figure ◽  
Power Level ◽  
Cmos Process ◽  
Conversion Gain ◽  
Input Frequency ◽  
Frequency Range ◽  
Shaping Technique ◽  
Active Mixer ◽  
Down Conversion ◽  
Second Order Nonlinearity

In this paper, a CMOS active down-conversion mixer is presented for wideband applications. Specifically, a LO generation chain is suggested to convert AC LO signal to shaped trapezoid burst, which reduces the sinusoidal LO power level requirement by the mixer. The current-reuse technique by stacked nMOS/pMOS architecture is used to save the power consumption of the circuit. Moreover, this complementary configuration is also employed to compensate second-order nonlinearity of the circuit. Implemented in a 0.18-[Formula: see text]m CMOS process, post-simulations show that, driven by only −10 dBm sinusoidal LO signal, the proposed inductorless mixer provides a maximal conversion gain of 15.7 dB and a noise figure (NF) of 9.1–12 dB across RF input frequency range 0.5–1.6 GHz. The IIP3 and IP1dB of 3.5 dBm and −4.8 dBm are obtained, respectively. The mixer core only consumes 3.6 mW from a 1.8-V supply.

scholarly journals A 1 to 32 GHz broadband multi-octave receiver for monolithic integrated vector network analyzers in SiGe technology

2018 ◽  
Vol 10 (5-6) ◽  
pp. 717-728
Author(s):  
Marco Dietz ◽  
Andreas Bauch ◽  
Klaus Aufinger ◽  
Robert Weigel ◽  
Amelie Hagelauer
Keyword(s):  
Noise Figure ◽  
Gain Control ◽  
Wide Frequency Range ◽  
Low Noise ◽  
Vector Network Analyzer ◽  
Ultra Wideband ◽  
Network Analyzer ◽  
Active Mixer ◽  
Input Matching ◽  
Better Than

AbstractA multi-octave receiver chain is presented for the use in a monolithic integrated vector network analyzer. The receiver exhibits a very wide frequency range of 1–32 GHz, where the gain meets the 3 dB-criterion. The differential receiver consists of an ultra-wideband low noise amplifier, an active mixer and an output buffer and exhibits a maximum conversion gain (CG) of 16.6 dB. The main design goal is a very flat CG over five octaves, which eases calibration of the monolithic integrated vector network analyzer. To realize variable gain functionality, without losing much input matching, an extended gain control circuit with additional feedback branch is shown. For the maximum gain level, a matching better than −10 dB is achieved between 1–28 GHz, and up to 30.5 GHz the matching is better than −8.4 dB. For both, the input matching and the gain of the LNA, the influence of the fabrication tolerances are investigated. A second gain control is implemented to improve isolation. The measured isolations between RF-to-LO and LO-to-RF are better than 30 dB and 60 dB, respectively. The LO-to-IF isolation is better than 35 dB. The noise figure of the broadband receiver is between 4.6 and 5.8 dB for 4–32 GHz and the output referred 1-dB-compression-point varies from 0.1 to 4.3 dBm from 2–32 GHz. The receiver draws a current of max. 66 mA at 3.3 V.

Design of Low-Noise Two-Path Amplifier for 6–16 GHz Applications

2020 ◽  
pp. 2150136
Author(s):  
Asieh Parhizkar Tarighat ◽  
Mostafa Yargholi
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Input Matching ◽  
Inductive Peaking ◽  
Linearity Improvement ◽  
Noise Amplifier ◽  
Path Structure

A two-path low-noise amplifier (LNA) is designed with TSMC 0.18[Formula: see text][Formula: see text]m standard RF CMOS process for 6–16[Formula: see text]GHz frequency band applications. The principle of a conventional resistive shunt feedback LNA is analyzed to demonstrate the trade-off between the noise figure (NF) and the input matching. To alleviate the mentioned issue for wideband application, this structure with noise canceling technique and linearity improvement are applied to a two-path structure. Flat and high gain is supplied by the primary path; while the input and output impedance matching are provided by the secondary path. The [Formula: see text][Formula: see text]dB bandwidth can be increased to a higher frequency by inductive peaking, which is used at the first stage of the two paths. Besides, by biasing the transistors at the threshold voltage, low power dissipation is achieved. The [Formula: see text][Formula: see text]dB gain bandwidth of the proposed LNA is 10[Formula: see text]GHz, while the maximum power gain of 13.1[Formula: see text]dB is attained. With this structure, minimum NF of 4.6[Formula: see text]dB and noise flatness of 1[Formula: see text]dB in the whole bandwidth can be achieved. The input impedance is matched, and S[Formula: see text] is lower than [Formula: see text]10 dB. With the proposed linearized LNA, the average IIP[Formula: see text][Formula: see text]dBm is gained, while it occupies 1051.7[Formula: see text][Formula: see text]m die area.

scholarly journals Design and Simulation Study of Active Baluns Circuits for WiMAX Applications

2019 ◽  
Vol 7 (1) ◽  
Author(s):  
Frederick Ray I. Gomez ◽  
John Richard E. Hizon ◽  
Maria Theresa G. De Leon
Keyword(s):  
Phase Difference ◽  
Simulation Study ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Cmos Process ◽  
Common Gate ◽  
Active Balun

The paper presents a design and simulation study of three active balun circuits implemented in a standard 90nm Complementary Metal-Oxide Semiconductor (CMOS) process namely: (1) common-source/drain active balun; (2) common-gate with common-source active balun; and (3) differential active balun.  The active balun designs are intended for Worldwide Interoperability for Microwave Access (WiMAX) applications operating at frequency 5.8GHz and with supply voltage of 1V.  Measurements are taken for parameters such as gain difference, phase difference, and noise figure.  All designs achieved gain difference of less than 0.23dB, phase difference of 180° ± 7.1°, and noise figure of 7.2–9.85dB, which are comparable to previous designs and researches.  Low power consumption attained at the most 4.45mW.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

2021 ◽  
Vol 18 (4) ◽  
pp. 1327-1330
Author(s):  
S. Manjula ◽  
R. Karthikeyan ◽  
S. Karthick ◽  
N. Logesh ◽  
M. Logeshkumar
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Design System ◽  
Cmos Process ◽  
Design Specifications ◽  
Noise Amplifier

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

A speed-optimized, low-noise APD with 0.18 μm CMOS technology for the VLC applications

2020 ◽  
Vol 34 (29) ◽  
pp. 2050321
Author(s):  
Wei Wang ◽  
Hong-An Zeng ◽  
Fang Wang ◽  
Guanyu Wang ◽  
Yingtao Xie ◽  
...  
Keyword(s):  
Dark Current ◽  
Complementary Metal Oxide Semiconductor ◽  
Visible Light Communication ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Excess Noise ◽  
Avalanche Breakdown ◽  
Cmos Process ◽  
Noise Characteristics

A new avalanche photodiode device applied to a visible light communication (VLC) system is designed using a standard 0.18 [Formula: see text]m complementary metal oxide semiconductor process. Compared to regular CMOS APD devices, the proposed device adds a [Formula: see text]-well layer above the deep [Formula: see text]-well/[Formula: see text]-substrate structure, and an [Formula: see text]/[Formula: see text] layer is deposited upon it. The [Formula: see text]/[Formula: see text] layer acts as an avalanche breakdown layer of the device, and an STI structure is used to prevent the edge break prematurely. The simulation results shows that the avalanche breakdown voltage is as low as 9.9 V, dark current is below [Formula: see text] A under −9.5 V bias voltage, and the 3 dB bandwidth is of 5.9 GHz. It is due to the use of the 0.18 [Formula: see text]m CMOS process-specific STI protection ring and short-circuits the connection of the deep [Formula: see text]-well/[Formula: see text]-substrate, and the dark current is reduced to be lower than two orders of magnitude compared to regular CMOS APD. Gain and noise characteristics are accurately calculated from Hayat dead-space model applied to this CMOS APD. So, this device’s gain and excess noise factor are 20 and 2.5, respectively.

An ESD Protected Wideband CMOS Low Noise Amplifier Employing Active Feedback Technique

2011 ◽  
Vol 403-408 ◽  
pp. 2809-2813
Author(s):  
Kuan Bao ◽  
Xiang Ning Fan
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Fully Integrated ◽  
Input Matching ◽  
Active Feedback ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
On Chip

This paper presents a wideband low noise amplifier (LNA) for multi-standard radio applications. The low noise characteristic and input matching are simultaneously achieved by active-feedback technique. Bond-wire inductors and electrostatic devices (ESDs) are co-designed to improve the chip performance. Implemented in 0.18-μm CMOS process, the core size of the fully integrated LNA circuits is 535 μm×425 μm without any passive on-chip inductor. The simulated gain and the minimal noise figure of the CMOS LNA are 17.5 dB and 2.0 dB, respectively. The LNA achieves a -3dB bandwidth of 3.1 GHz. And the simulated IIP3 is -4.4 dBm at 2.5 GHz. Operating at 1.8V, the LNA draws a current of 7.7 mA.

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