A NOVEL FPGA-BASED APPROACH FOR DIGITAL WAVEFORM GENERATION USING ORTHOGONAL FUNCTIONS

2007 ◽  
Vol 16 (06) ◽  
pp. 895-909 ◽  
Author(s):  
SYED MANZOOR QASIM ◽  
SHUJA AHMAD ABBASI
Keyword(s):  
High Speed ◽  
Cost Effective ◽  
Digital Design ◽  
Waveform Generator ◽  
Orthogonal Functions ◽  
Orthogonal Function ◽  
Waveform Generation ◽  
Novel Approach ◽  
Field Programmable ◽  
On Chip

This paper presents a novel approach for the generation of periodic waveforms in digital form using Field Programmable Gate Array (FPGA) and orthogonal functions. The orthogonal function consists of a set of Rademacher–Walsh Functions, and utilizing these functions, virtually any periodic waveform can be synthesized. Recent technological advancements in FPGA and availability of sophisticated digital design tools have made it possible to realize high-speed waveform generator in a cost-effective way. We demonstrate the proposed technique for the successful generation of Trapezoidal, Sinusoidal, Triangular waveforms, and a complex version of these waveforms. Simulation results for the various waveforms implemented in Xilinx Spartan-3 (XC3S200-4FT256) FPGA are presented both in analog and digital forms, and validated in MATLAB. The designed circuit can be easily integrated as a module for System-on-Chip (SoC) for on-chip waveform generation

Fifty years of Electronic Hardware Implementations of First and Higher Order Neural Networks

2010 ◽  
pp. 269-285 ◽  
Author(s):  
David R. Selviah ◽  
Janti Shawash
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
High Speed ◽  
Higher Order ◽  
Low Latency ◽  
Real Time Control ◽  
Practical Applications ◽  
Field Programmable ◽  
On Chip ◽  
Electronic Hardware

This chapter celebrates 50 years of first and higher order neural network (HONN) implementations in terms of the physical layout and structure of electronic hardware, which offers high speed, low latency, compact, low cost, low power, mass produced systems. Low latency is essential for practical applications in real time control for which software implementations running on CPUs are too slow. The literature review chapter traces the chronological development of electronic neural networks (ENN) discussing selected papers in detail from analog electronic hardware, through probabilistic RAM, generalizing RAM, custom silicon Very Large Scale Integrated (VLSI) circuit, Neuromorphic chips, pulse stream interconnected neurons to Application Specific Integrated circuits (ASICs) and Zero Instruction Set Chips (ZISCs). Reconfigurable Field Programmable Gate Arrays (FPGAs) are given particular attention as the most recent generation incorporate Digital Signal Processing (DSP) units to provide full System on Chip (SoC) capability offering the possibility of real-time, on-line and on-chip learning.

scholarly journals ANALYSIS OF EFFECTS OF USING 9/7 WAVELET COEFFICIENTS IN MULTI-RESOLUTION ANALYSIS

2016 ◽  
Vol 2 (1) ◽  
Author(s):  
Manish Sharma ◽  
Prof. Sonu Lal
Keyword(s):  
High Speed ◽  
Utilization Efficiency ◽  
Parallel Structure ◽  
Discrete Wavelet ◽  
Distributed Arithmetic ◽  
Fpga Design ◽  
Multi Resolution Analysis ◽  
Field Programmable ◽  
On Chip ◽  
Area Efficient

Conventional distributed arithmetic (DA) is popular in field programmable gate array (FPGA) design, and it features on-chip ROM to achieve high speed and regularity. In this paper, we describe high speed area efficient 1-D discrete wavelet transform (DWT) using 9/7 filter based new efficient distributed arithmetic (NEDA) Technique. Being area efficient architecture free of ROM, multiplication, and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. This architecture supports any size of image pixel value and any level of decomposition. The parallel structure has 100% hardware utilization efficiency.

scholarly journals Integrated Photonics Based High Speed Arbitrary Waveform Generation

2021 ◽  
Author(s):  
Shivangi Chugh ◽  
Shalabh Gupta
Keyword(s):  
High Speed ◽  
Photonic Integration ◽  
Waveform Generator ◽  
Digital To Analog Converter ◽  
Arbitrary Waveform Generation ◽  
Waveform Generation ◽  
Silicon Photonic ◽  
Bandwidth Limitation ◽  
High Bandwidth ◽  
Arbitrary Waveform

High speed arbitrary waveform generator enabled by photonic digital to analog converter where the bandwidth limitation arising due to interconnect and device parasitics in its electronic counterparts is circumvented. Leveraging the silicon photonic integration technology for this purpose provides a potential high resolution, high bandwidth, and energy efficient solution for signal transmitters.

A Method on Realizing Signal Generator for Arbitrary Waveform

2013 ◽  
Vol 333-335 ◽  
pp. 661-665
Author(s):  
Deng Rong Zhou ◽  
Yu Rong Zhou ◽  
Jian Chun Gong ◽  
Da Xing Chen
Keyword(s):  
High Speed ◽  
Synthesis Method ◽  
Sine Wave ◽  
Waveform Generator ◽  
Direct Digital Synthesis ◽  
Waveform Data ◽  
Field Programmable ◽  
Digital Synthesis ◽  
Arbitrary Waveform ◽  
Hardware Circuit

The basic approach of generating arbitrary waveform is the digital synthesis method. Appling this method, one first samples and quantifies a period of the signal waveform to be generized, memorizes the obtained binary waveform data in a memory, and then reads it via hardware circuit in certain sequence, converts the data via digital-to-analog (DA) circuit, finally output the analog waveform through a filter. In this work, an arbitrary waveform generator (AWG) is designed based on the theory of direct digital synthesis (DDS)[1-7]and on the analysis of the performance of the output signal. The design uses a field programmable-gate-array (FPGA)[3]chip to utilize the AWG. The preset and display of the output frequency and phase are controlled by a micro computer unit (MCU). The artribary waveform data can be downloaded and updated from a communication interface. The AWG can produce a high-resolution arbitrary waveform. The dissertation focuses on hardware circuit design, which has been accomplished, including power supply module, MCU system, high-speed DA converter, and filter, etc. The experimental prototype of the AWG has been made and tested systemly.At the end of the dissertation, the measurement result of the system is given and its error is analyzed. It is shown the AWG can output a sine wave, a triangle wave, a sawteeth wave, or a square wave within the frequency range from 0.01Hz to 15MHz with the step of 10mHz, or output an arbitrary waveform within the range from 0.01Hz to 20kHz.

scholarly journals Dynamic Task Distribution Model for On-Chip Reconfigurable High Speed Computing System

2015 ◽  
Vol 2015 ◽  
pp. 1-12
Author(s):  
Mahendra Vucha ◽  
Arvind Rajawat
Keyword(s):  
High Speed ◽  
High Performance ◽  
Real Life ◽  
Computing System ◽  
Distribution Model ◽  
Design Parameters ◽  
Dynamic Task ◽  
Task Distribution ◽  
Field Programmable ◽  
On Chip

Modern embedded systems are being modeled as Reconfigurable High Speed Computing System (RHSCS) where Reconfigurable Hardware, that is, Field Programmable Gate Array (FPGA), and softcore processors configured on FPGA act as computing elements. As system complexity increases, efficient task distribution methodologies are essential to obtain high performance. A dynamic task distribution methodology based on Minimum Laxity First (MLF) policy (DTD-MLF) distributes the tasks of an application dynamically onto RHSCS and utilizes available RHSCS resources effectively. The DTD-MLF methodology takes the advantage of runtime design parameters of an application represented as DAG and considers the attributes of tasks in DAG and computing resources to distribute the tasks of an application onto RHSCS. In this paper, we have described the DTD-MLF model and verified its effectiveness by distributing some of real life benchmark applications onto RHSCS configured on Virtex-5 FPGA device. Some benchmark applications are represented as DAG and are distributed to the resources of RHSCS based on DTD-MLF model. The performance of the MLF based dynamic task distribution methodology is compared with static task distribution methodology. The comparison shows that the dynamic task distribution model with MLF criteria outperforms the static task distribution techniques in terms of schedule length and effective utilization of available RHSCS resources.

scholarly journals Cost Effective Implementation of Fixed Point Adders for LUT based FPGAs using Technology Dependent Optimizations

2015 ◽  
Vol 19 (1) ◽  
pp. 14 ◽  
Author(s):  
Burhan Khurshid ◽  
Roohie Naaz
Keyword(s):  
Fixed Point ◽  
Critical Path ◽  
Minimum Cost ◽  
Cost Effective ◽  
Path Delay ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Volume Production ◽  
On Chip ◽  
The Cost

Modern day field programmable gate arrays(FPGAs) have very huge and versatile logic resources resulting inthe migration of their application domain from prototypedesigning to low and medium volume production designing.Unfortunately most of the work pertaining to FPGAimplementations does not focus on the technology dependentoptimizations that can implement a desired functionality withreduced cost. In this paper we consider the mapping of simpleripple carry fixed-point adders (RCA) on look-up table (LUT)based FPGAs. The objective is to transform the given RCABoolean network into an optimized circuit netlist that canimplement the desired functionality with minimum cost. Weparticularly focus on 6-input LUTs that are inherent in all themodern day FPGAs. Technology dependent optimizations arecarried out to utilize this FPGA primitive efficiently and theresult is compared against various adder designs. Theimplementation targets the XC5VLX30-3FF324 device fromXilinx Virtex-5 FPGA family. The cost of the circuit is expressedin terms of the resources utilized, critical path delay and theamount of on-chip power dissipated. Our implementation resultsshow a reduction in resources usage by at least 50%; increase inspeed by at least 10% and reduction in dynamic powerdissipation by at least 30%. All this is achieved without anytechnology independent (architectural) modification.

A Novel Approach to 3D Chip Stacking

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000797-000816
Author(s):  
Mark Vandermeulen ◽  
Andrew Smith ◽  
Ron Csermak
Keyword(s):  
Cost Effective ◽  
Passive Components ◽  
Design Flexibility ◽  
Novel Approach ◽  
3D Packaging ◽  
Cost Effective Alternative ◽  
On Chip ◽  
The Cost ◽  
Vertical Interconnect ◽  
3D Chip Stacking

Designers seeking electronic package miniaturization but lacking the resources to utilize custom ASIC or complex 3D integration approaches can now take advantage of chip stacking technology for integrating a range of devices into small, system-in-package (SiP) structures. A robust, innovative approach, suitable for supporting low- to medium-volume applications, has been developed which avoids the cost and/or size penalties typically encountered using traditional multi-chip packaging techniques. Using bare die and vertical interconnect/interposer structures, this stacking technology permits the design of multi-chip assemblies with either identical or dissimilar die, co-packaged with discrete and/or integrated passive devices. The approach is independent of ASIC foundry process and does not require through-silicon via (TSV) technology, and is therefore well-suited for designs incorporating multiple IC's from different semiconductor processes or manufacturing sources. Relative to system-on-chip (SoC) ASIC implementations, which carry large upfront NRE costs and long development cycles, 3D co-packaging of heterogeneous devices in customized SiP packages offers a proven, cost-effective alternative with greater design flexibility and reduced time to market. This presentation will describe this novel 3D packaging approach, and how it can be used in conjunction with discrete and integrated passive components to address package designs where size, weight, and/or performance are at a premium.

Tunable Microring Filter Based On-Chip Interrogator for Wavelength-Modulated Optical Sensor

2013 ◽  
Vol 562-565 ◽  
pp. 265-267 ◽  
Author(s):  
Jian Yang ◽  
Chen Qiu ◽  
Qi Long Wang ◽  
Ming Hua Wang ◽  
Jian Yi Yang
Keyword(s):  
Optical Sensors ◽  
Optical Sensor ◽  
Cost Effective ◽  
Center Wavelength ◽  
Novel Approach ◽  
On Chip

We demonstrated a novel approach for the interrogation of wavelength-modulated optical sensors. The interrogator is based on a tunable on-chip microring filter. By tuning the center wavelength of the microring filter, the center wavelength of the sensor can be readout by the corresponding tuning power. This approach has the potential of constructing a compact and cost-effective interrogator with good performance.

Low-Power High-Performance Tunnel FET With Analysis for IoT Applications

2020 ◽  
pp. 47-67 ◽  
Author(s):  
Suman Lata Tripathi
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Digital Design ◽  
Iot Applications ◽  
Reduction Techniques ◽  
Tunnel Fet ◽  
Harvesting Systems ◽  
On Chip ◽  
Memory Applications

The emerging tunnel FET is analysed in terms of ON-state current, OFF-state current, subthreshold slope, switching capacitance to explore its applications for smaller size low-power high-speed digital and memory applications that are an integral part of portable intelligent devices for IoT applications. A large portion of IoT systems are associated with these embedded SRAM/DRAM memories that contribute to a major portion of power dissipation in systems-on-chip (SoCs) or digital design. Several SRAM cell-based memory designs with TFET structures are compared to focus their applications. The ambilpolar nature of TFET structures are investigated for highly random, unclonable secured hardware systems. New circuit designs with TFET were explored for turn-on voltage reduction, ON-state resistance reduction, and reverse leakage reduction techniques that plays an important role in designing efficient energy-harvesting systems.

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