Aging-Aware Task Scheduling for Mesh-Based Network-on-Chips Under Aging Effect

2019 ◽  
Vol 28 (09) ◽  
pp. 1950146 ◽  
Author(s):  
Jinbin Tu ◽  
Tianhao Yang ◽  
Lu Yin ◽  
Shuangyu Xie ◽  
Ruitao Xu ◽  
...  
Keyword(s):  
Task Scheduling ◽  
Aging Effect ◽  
Performance Degradation ◽  
Path Delay ◽  
Negative Bias Temperature Instability ◽  
Processor Core ◽  
Bias Temperature Instability ◽  
Heuristic Scheduling ◽  
Scheduling Method ◽  
On Chip

The aging effect induced by negative bias temperature instability (NBTI) is a universal issue existing in electronic equipments. NBTI aging effect can increase the path delay of network-on-chip (NoC) device, resulting in the decreased frequency of processor core and in turn its performance degradation. Under this circumstance, aging-aware task scheduling becomes a complex and challenging problem in advanced multicore systems. This paper presents an aging-aware scheduling method that incorporates NBTI aging effect into the task scheduling framework for mesh-based NoCs. The proposed method relies on a NBTI aging model to evaluate the degradation of core’s operating frequency to establish the task scheduling model under aging effect. Taking into account core performance degradation and the communication overheads among cores, we develop a meta-heuristic scheduling strategy based on particle swarm optimization algorithm to minimize the total execution time of all tasks. Experimental results show that the schedule obtained by the aging-aware algorithm has shorter completion time and higher throughput compared with the nonaging-aware case. On average, the makespan can be reduced by 13.55% and the throughput can be increased by 21.73% for a variety of benchmark applications.

Reducing Design Margins by Adaptive Compensation for Thermal and Aging Variations

2012 ◽  
pp. 201-230
Author(s):  
Zhenyu Qi ◽  
Yan Zhang ◽  
Mircea Stan
Keyword(s):  
Design Parameters ◽  
Worst Case Analysis ◽  
Transimpedance Amplifier ◽  
Large Area ◽  
Negative Bias Temperature Instability ◽  
Worst Case ◽  
Adaptive Computation ◽  
Bias Temperature Instability ◽  
Computation Efficiency ◽  
On Chip

Corner-based design and verification are based on worst-case analysis, thus introducing over-pessimism and large area and power overhead and leading to unnecessary energy consumption. Typical case-based design and verification maximize energy efficiency through design margins reduction and adaptive computation, thus helping achieve sustainable computing. Dynamically adapting to manufacturing, environmental, and usage variations is the key to shaving unnecessary design margins, which requires on-chip modules that can sense and configure design parameters both globally and locally to maximize computation efficiency, and maintain this efficiency over the lifetime of the system. This chapter presents an adaptive threshold compensation scheme using a transimpedance amplifier and adaptive body biasing to overcome the effects of temperature variation, reliability degradation, and process variation. The effectiveness and versatility of the scheme are demonstrated with two example applications, one as a temperature aware design to maintain IONto IOFFcurrent ratio, the other as a reliability sensor for NBTI (Negative Bias Temperature Instability).

scholarly journals Countermeasures against NBTI degradation on 6T-SRAM cells

2011 ◽  
Vol 9 ◽  
pp. 255-261 ◽  
Author(s):  
E. Glocker ◽  
D. Schmitt-Landsiedel ◽  
S. Drapatz
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Aging Effect ◽  
Static Random Access Memory ◽  
Negative Bias Temperature Instability ◽  
Access Memory ◽  
Bias Temperature Instability ◽  
Simulation Results ◽  
Degradation Effect

Abstract. In current process technologies, NBTI (negative bias temperature instability) has the most severe aging effect on static random access memory (SRAM) cells. This degradation effect causes loss of stability. In this paper countermeasures against this hazard are presented and quantified via simulations in 90 nm process technologies by the established metrics SNMread, SNMhold, Iread and Write Level. With regard to simulation results and practicability best candidates are chosen and, dependent on individual preferences at memory cell design, the best countermeasure in each case is recommended.

NBTI-Aware Power Gating Design with Dynamically Varying Stress Probability Control on Sleep Transistor

2021 ◽  
pp. 2120004
Author(s):  
Abhishek Bhattacharjee ◽  
Sambhu Nath Pradhan
Keyword(s):  
Control Method ◽  
Logic Gates ◽  
Aging Effect ◽  
Threshold Value ◽  
Digital Circuit ◽  
Power Gating ◽  
Negative Bias Temperature Instability ◽  
Bias Temperature Instability ◽  
Device Parameter ◽  
Reliability Performance

With the aggressive scaling of the transistor, Negative Bias Temperature Instability (NBTI) has become the most dominant aging effect which causes the device parameter to degrade over its lifetime. This device parameter degradation of logic gates in nanometer technology is a major concern for the reliability of the digital circuit. It becomes even more critical when it comes to power gating structure, as small NBTI effect on PMOS sleep transistor used in header-based power gating structure would seriously affect the reliability, performance of the whole logic circuit. The conventional method of mitigating the NBTI effect is to oversize the sleep transistor, but it also gives rise to leakage overhead. In this work, a novel NBTI aware power gating architecture is presented to improve the lifetime of the circuit. Here, sleep transistors (STs) are switched ON/OFF periodically and a greater number of STs are turned ON, when NBTI related degradation reaches to its threshold value so that STs get more time to anneal NBTI degradation and improve its lifetime. Simulation result on ISCAS’85 benchmark circuits shows for 40% sleep signal, an average of 51.2% and 14% lifetime improvement with respect to the conventional over-sizing (OS) technique and normal stress probability control method, respectively with some power and area overhead.

Vth Extraction Based Run Time Transistor Width (TWOS) Module for On-Chip Negative Bias Temperature Instability (NBTI) Mitigation

2019 ◽  
Vol 17 (5) ◽  
pp. 385-392
Author(s):  
Vaibhav Neema ◽  
Kuldeep Raguwanshi ◽  
Ambika Prasad Shah ◽  
Santosh Kumar Vishvakarma
Keyword(s):  
Negative Bias ◽  
Negative Bias Temperature Instability ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
Run Time ◽  
On Chip

Reducing Design Margins by Adaptive Compensation for Thermal and Aging Variations

2012 ◽  
pp. 284-312
Author(s):  
Zhenyu Qi ◽  
Yan Zhang ◽  
Mircea Stan
Keyword(s):  
Design Parameters ◽  
Worst Case Analysis ◽  
Transimpedance Amplifier ◽  
Large Area ◽  
Negative Bias Temperature Instability ◽  
Worst Case ◽  
Adaptive Computation ◽  
Bias Temperature Instability ◽  
Computation Efficiency ◽  
On Chip

Corner-based design and verification are based on worst-case analysis, thus introducing over-pessimism and large area and power overhead and leading to unnecessary energy consumption. Typical case-based design and verification maximize energy efficiency through design margins reduction and adaptive computation, thus helping achieve sustainable computing. Dynamically adapting to manufacturing, environmental, and usage variations is the key to shaving unnecessary design margins, which requires on-chip modules that can sense and configure design parameters both globally and locally to maximize computation efficiency, and maintain this efficiency over the lifetime of the system. This chapter presents an adaptive threshold compensation scheme using a transimpedance amplifier and adaptive body biasing to overcome the effects of temperature variation, reliability degradation, and process variation. The effectiveness and versatility of the scheme are demonstrated with two example applications, one as a temperature aware design to maintain IONto IOFFcurrent ratio, the other as a reliability sensor for NBTI (Negative Bias Temperature Instability).

scholarly journals Aging-Resilient Topology Synthesis of Heterogeneous Manycore Network-On-Chip Using Genetic Algorithm with Flexible Number of Routers

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1458 ◽  
Author(s):  
Young Sik Lee ◽  
SoYoung Kim ◽  
Tae Hee Han
Keyword(s):  
Genetic Algorithm ◽  
Network Connectivity ◽  
Aging Effect ◽  
Network On Chip ◽  
Carrier Injection ◽  
Hot Carrier ◽  
Bias Temperature Instability ◽  
Nanoscale System ◽  
Average Latency ◽  
On Chip

As semiconductor processes enter the nanoscale, system-on-chip (SoC) interconnects suffer from link aging owing to negative bias temperature instability (NBTI), hot carrier injection (HCI), and electromigration. In network-on-chip (NoC) for heterogeneous manycore systems, there is a difference in the aging speed of links depending on the location and utilization of resources. In this paper, we propose a heterogeneous manycore NoC topology synthesis that predicts the aging effect of each link and deploys routers and error correction code (ECC) logic. Aging-aware ECC logic is added to each link to achieve the same link lifetime with less area and latency than the Bose-Chaudhuri-Hocquenghem (BCH) logic. Moreover, based on the modified genetic algorithm, we search for a solution that minimizes the average latency while ensuring the link lifetime by changing the number of routers, location, and network connectivity. Simulation results demonstrate that the aging-aware topology synthesis reduces the average latency of the network by up to 26.68% compared with the aging analysis and the addition of ECC logic on the link after the topology synthesis. Furthermore, topology synthesis with aging-aware ECC logic reduces the maximum average latency by up to 39.49% compared with added BCH logic.

scholarly journals Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 346 ◽  
Author(s):  
Lili Shen ◽  
Ning Wu ◽  
Gaizhen Yan
Keyword(s):  
Power Consumption ◽  
Thermal Management ◽  
System Performance ◽  
Control Policy ◽  
Three Dimension ◽  
Processor Core ◽  
Management Scheme ◽  
And Performance ◽  
On Chip ◽  
Silicon Vias

By using through-silicon-vias (TSV), three dimension integration technology can stack large memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory access and enhance system performance. However, the integration of more on-chip caches increases chip power density, which might lead to temperature-related issues in power consumption, reliability, cooling cost, and performance. An effective thermal management scheme is required to ensure the performance and reliability of the system. In this study, a fuzzy-based thermal management scheme (FBTM) is proposed that simultaneously considers cores and stacked caches. The proposed method combines a dynamic cache reconfiguration scheme with a fuzzy-based control policy in a temperature-aware manner. The dynamic cache reconfiguration scheme determines the size of the cache for the processor core according to the application that reaches a substantial amount of power consumption savings. The fuzzy-based control policy is used to change the frequency level of the processor core based on dynamic cache reconfiguration, a process which can further improve the system performance. Experiments show that, compared with other thermal management schemes, the proposed FBTM can achieve, on average, 3 degrees of reduction in temperature and a 41% reduction of leakage energy.

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