A Digital-Based Ultra-Low-Voltage Pseudo-Differential CMOS Schmitt Trigger

2019 ◽  
Vol 29 (04) ◽  
pp. 2020002
Author(s):  
Yasin Bastan ◽  
Parviz Amiri
Keyword(s):  
Integrated Circuit ◽  
Low Voltage ◽  
Design Procedure ◽  
Schmitt Trigger ◽  
Input Voltage ◽  
Cmos Process ◽  
Differential Mode ◽  
Digital Cmos ◽  
Hysteresis Width ◽  
Chip Area

A digital-based Pseudo-differential Schmitt trigger is proposed in this paper which is suitable for ultra-low voltages and pure digital integrated circuit technologies. The proposed Schmitt trigger is implemented according to the design procedure of an analog Schmitt trigger and only using digital CMOS inverters. It is composed of a differential comparator consisting of two CMOS inverters and a cross-coupled inverter pair positive feedback which has simultaneously two outputs of noninverting and inverting. The proposed circuit is the only digital Schmitt trigger which operates in differential mode and its hysteresis center can be changed by the input voltage. Implementing the circuit in digital-based allows the proposed Schmitt trigger to operate in 0.4[Formula: see text]V ultra-low-voltage. Principle operation of the proposed circuit is discussed theoretically and using formulas and its performance is verified by simulation in TSMC 0.18[Formula: see text][Formula: see text]m CMOS process. The proposed circuit occupies only [Formula: see text][Formula: see text][Formula: see text]m2 chip area due to the very low number of transistors. The hysteresis width of the proposed Schmitt trigger is 205[Formula: see text]mV and consumes only 6.64[Formula: see text]nW power.

A Low-Voltage Bulk-Driven Differential CMOS Schmitt Trigger with Tunable Hysteresis

2019 ◽  
Vol 28 (07) ◽  
pp. 1920004 ◽  
Author(s):  
Ali Nejati ◽  
Yasin Bastan ◽  
Parviz Amiri ◽  
Mohammad Hossein Maghami
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Schmitt Trigger ◽  
Noise Removal ◽  
Cmos Process ◽  
Current Feedback ◽  
Silicon Area ◽  
Hysteresis Width ◽  
Common Mode Voltage ◽  
Simulation Results

This paper describes a low-voltage bulk-driven differential CMOS Schmitt trigger with tunable hysteresis for use in noise removal applications. The hysteresis of the proposed Schmitt trigger is designed based on a regenerative current feedback and its width is adjustable by two control voltages. The center of the hysteresis can also be adjusted by either the control voltages or input common-mode voltage. The principle operation of the proposed circuit is discussed, its main formulas are derived and its performance is verified by Cadence post-layout simulations. Designed in the TSMC 0.18[Formula: see text][Formula: see text]m standard CMOS process, the circuit consumes [Formula: see text]m2 of silicon area. Post-layout simulation results indicate that the hysteresis width of the Schmitt trigger can be adjusted from 170 to 270[Formula: see text]mV and the ratio of the hysteresis width variation to supply voltage is 11.11%. Operated with 0.8[Formula: see text]V supply voltage, the power consumption of the circuit ranges from 0.48 to 1.12[Formula: see text]mW.

scholarly journals Design of a Low Voltage Schmitt Trigger in 0.18 um CMOS Process With Tunable Hysteresis

2013 ◽  
Vol 7 (4) ◽  
Author(s):  
Haroon Rashid ◽  
Md. Mamun ◽  
Md. Syedul Amin ◽  
Hafizah Husain
Keyword(s):  
Low Voltage ◽  
Schmitt Trigger ◽  
Cmos Process

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

2.2–4.6-GHz Active Quasi-Circulator with > 24-dB Transmit–Receive Isolation

2019 ◽  
Vol 29 (05) ◽  
pp. 2050077
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Danish Kaleem ◽  
Zhi-Gong Wang ◽  
Keping Wang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
The Body ◽  
Common Source ◽  
Cmos Process ◽  
Secondary Effects ◽  
Body Effect ◽  
Chip Area ◽  
Common Gate ◽  
Loading Effects ◽  
Better Than

An active quasi-circulator (AQC) integrated circuit is designed and fabricated in a 0.18-[Formula: see text]m CMOS process. The proposed design is based on a parallel combination of a common-source (CS) stage and a combined common-drain (CD) and common-gate (CG) topology. Scattering matrix of the core AQC circuit is derived considering MOSFET’s secondary effects, particularly the body effect as well as output loading effects. Measurements of the quasi-circulator reveal an insertion loss of [Formula: see text] dB between transmitter-to-antenna ports ([Formula: see text]) and of [Formula: see text] dB between antenna-to-receiver ports ([Formula: see text]), within a frequency band of 2.2–4.6 GHz. The isolation between the transmitter and the receiver ports ([Formula: see text]) is better than 24 dB with a maximum value of 29.5[Formula: see text]dB @ 3.6[Formula: see text]GHz. The power dissipation of the proposed AQC is 40[Formula: see text]mW and it covers an active chip area of 0.677[Formula: see text]mm2.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

A TIME-DOMAIN 1.0-V/0.8-MW 6-BIT 125 MS/S FLASH ADC IN 65 NM CMOS

2013 ◽  
Vol 22 (04) ◽  
pp. 1350017 ◽  
Author(s):  
GUANZHONG HUANG ◽  
PINGFEN LIN
Keyword(s):  
Time Domain ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Sampling Rate ◽  
Digital Signal ◽  
Input Voltage ◽  
Gray Code ◽  
Digital Circuit ◽  
Cmos Process ◽  
Flash Adc

A 6-bit low-voltage power-efficient flash analog-to-digital converter (ADC) is presented in this paper. The proposed ADC replaces the conventional voltage comparator with a new approach in the time-domain. The reference voltages and the analog input voltage are converted to digital signal in a form of different pulse widths by using a pulse-width-modulation (PWM) circuit. Consequently, the comparison is achieved by checking the sequence of the pulse rising edges rather than amplifying and latching the voltage difference. The total input capacitance of the proposed ADC is as small as tens of femto-farads, resulting in much less demand for the front-end buffer and the sampling switch. In addition, an implementation of the digital foreground calibration helps to get rid of the nonmonotonic comparison thresholds due to mismatch. The calibration operates with the adaptive comparison threshold by tuning the modulation level of the PWM. The intermediate Gray code conversion increases the bubble tolerance by 1LSB. This digital-circuit-heavily-involved ADC has been designed and simulated in a 65 nm CMOS process, achieving 35.24 dB signal-to-noise-and-distortion-ratio (SNDR) at a sampling rate of 125 MS/s while consuming 803 μW from 1 V power supply. As a result, the figure of merit (FoM) is as low as 136 fJ/conversion-step.

A 1.2 V 15–32 GHz low-power single-balanced gate mixer with a miniature rat-race hybrid

2012 ◽  
Vol 4 (4) ◽  
pp. 455-461
Author(s):  
Chung-Chun Chen ◽  
Chun-Hsien Lien ◽  
Hen-Wai Tsao ◽  
Huei Wang
Keyword(s):  
Power Consumption ◽  
Design Procedure ◽  
Local Oscillator ◽  
Cmos Technology ◽  
Conversion Gain ◽  
Conversion Loss ◽  
Power Budget ◽  
Digital Cmos ◽  
Chip Area ◽  
Dc Power

A 15–32 GHz miniature single-balanced gate mixer is proposed and analyzed. It achieves a smaller chip area with acceptable conversion gain and port-to-port isolation. In addition, the design procedure is described in detail. This mixer, fabricated in 90 nm digital CMOS technology, demonstrates a measured conversion loss of 1 dB and higher than 30 dB RF-to-LO port isolation from 17 to 32 GHz, at a local oscillator (LO) driver power of −4.3 dBm. The total dc power consumption is only 6 mW from a 1.2 V supply, including output buffer. The low dc power consumption and LO driver power reduce the power budget, and the proposed miniature rat-race hybrid facilitates integration in a receiver.

Fabrication of microbridges in standard complementary metal oxide semiconductor technology

1989 ◽  
Vol 67 (4) ◽  
pp. 184-189 ◽  
Author(s):  
M. Parameswaran ◽  
Lj. Ristic ◽  
A. C. Dhaded ◽  
H. P. Baltes ◽  
W. Allegretto ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Layout Design ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Digital Cmos ◽  
Sensor Applications

Complementary metal oxide semiconductor (CMOS) technology is one of the leading fabrication technologies of the semiconductor integrated-circuit industry. We have discovered features inherent in the standard CMOS fabrication process that lend themselves to the manufacturing of micromechanical structures for sensor applications. In this paper we present an unconventional layout design methodology that allows us to exploit the standard CMOS process for producing microbridges. Two types of microbridges, bare polysilicon microbridges and sandwiched oxide microbridges, have been manufactured by first implementing a special layout design in an industrial digital CMOS process, followed by a postprocessing etching step.

scholarly journals Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

2020 ◽  
Vol 15 (1) ◽  
Author(s):  
Ruibo Chen ◽  
Hongxia Liu ◽  
Wenqiang Song ◽  
Feibo Du ◽  
Hao Zhang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Voltage ◽  
Cmos Technology ◽  
Cmos Process ◽  
Triggering Mechanism ◽  
Esd Protection ◽  
Tcad Simulation ◽  
P Type ◽  
28 Nm ◽  
Latch Up

Abstract Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

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