A Low-Voltage Bulk-Driven Differential CMOS Schmitt Trigger with Tunable Hysteresis

2019 ◽  
Vol 28 (07) ◽  
pp. 1920004 ◽  
Author(s):  
Ali Nejati ◽  
Yasin Bastan ◽  
Parviz Amiri ◽  
Mohammad Hossein Maghami
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Schmitt Trigger ◽  
Noise Removal ◽  
Cmos Process ◽  
Current Feedback ◽  
Silicon Area ◽  
Hysteresis Width ◽  
Common Mode Voltage ◽  
Simulation Results

This paper describes a low-voltage bulk-driven differential CMOS Schmitt trigger with tunable hysteresis for use in noise removal applications. The hysteresis of the proposed Schmitt trigger is designed based on a regenerative current feedback and its width is adjustable by two control voltages. The center of the hysteresis can also be adjusted by either the control voltages or input common-mode voltage. The principle operation of the proposed circuit is discussed, its main formulas are derived and its performance is verified by Cadence post-layout simulations. Designed in the TSMC 0.18[Formula: see text][Formula: see text]m standard CMOS process, the circuit consumes [Formula: see text]m2 of silicon area. Post-layout simulation results indicate that the hysteresis width of the Schmitt trigger can be adjusted from 170 to 270[Formula: see text]mV and the ratio of the hysteresis width variation to supply voltage is 11.11%. Operated with 0.8[Formula: see text]V supply voltage, the power consumption of the circuit ranges from 0.48 to 1.12[Formula: see text]mW.

scholarly journals A Sub-Threshold Differential CMOS Schmitt Trigger with Adjustable Hysteresis Based on Body Bias Technique

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 806
Author(s):  
Sara Radfar ◽  
Ali Nejati ◽  
Yasin Bastan ◽  
Parviz Amiri ◽  
Mohammad Hossein Maghami ◽  
...  
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Schmitt Trigger ◽  
The Body ◽  
Cmos Process ◽  
Electronic Systems ◽  
Silicon Area ◽  
Hysteresis Width ◽  
Suitable Candidate ◽  
Body Bias

This paper presents a sub-threshold differential CMOS Schmitt trigger with tunable hysteresis, which can be used to enhance the noise immunity of low-power electronic systems. By exploiting the body bias technique to the positive feedback transistors, the hysteresis of the proposed Schmitt trigger is generated, and it can be adjusted by the applied bias voltage to the bulk terminal of the utilized PMOS transistors. The principle of operation and the main formulas of the proposed circuit are discussed. The circuit is designed in a 0.18-μm standard CMOS process with a 0.6 V power supply. Post-layout simulation results show that the hysteresis width of the Schmitt trigger can be adjusted from 45.5 mV to 162 mV where the ratio of the hysteresis width variation to supply voltage is 19.4%. This circuit consumes 10.52 × 7.91 μm2 of silicon area, and its power consumption is only 1.38 µW, which makes it a suitable candidate for low-power applications such as portable electronic, biomedical, and bio-implantable systems.

A 16.4 nW, Sub-1 V, Resistor-Less Voltage Reference with BJT Voltage Divider

2018 ◽  
Vol 27 (13) ◽  
pp. 1850206 ◽  
Author(s):  
Qingshan Yang ◽  
Peiqing Han ◽  
Niansong Mei ◽  
Zhaofeng Zhang
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Divider ◽  
Total Power ◽  
Cmos Process ◽  
Operating Voltage ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Total Power Consumption

A 16.4[Formula: see text]nW, sub-1[Formula: see text]V voltage reference for ultra-low power low voltage applications is proposed. This design reduces the operating voltage to 0.8[Formula: see text]V by a BJT voltage divider and decreases the silicon area considerably by eliminating resistors. The PTAT and CTAT are based on SCM structures and a scaled-down [Formula: see text], respectively, to improve the process insensitivity. This work is fabricated in 0.18[Formula: see text][Formula: see text]m CMOS process with a total area of 0.0033[Formula: see text]mm2. Measured results show that it works properly for supply voltage from 0.8[Formula: see text]V to 2[Formula: see text]V. The reference voltage is 467.2[Formula: see text]mV with standard deviation ([Formula: see text]) being 12.2 mV and measured TC at best is 38.7[Formula: see text]ppm/[Formula: see text]C ranging from [Formula: see text]C to 60[Formula: see text]C. The total power consumption is 16.4[Formula: see text]nW under the minimum supply voltage at 27[Formula: see text]C.

A Digital-Based Ultra-Low-Voltage Pseudo-Differential CMOS Schmitt Trigger

2019 ◽  
Vol 29 (04) ◽  
pp. 2020002
Author(s):  
Yasin Bastan ◽  
Parviz Amiri
Keyword(s):  
Integrated Circuit ◽  
Low Voltage ◽  
Design Procedure ◽  
Schmitt Trigger ◽  
Input Voltage ◽  
Cmos Process ◽  
Differential Mode ◽  
Digital Cmos ◽  
Hysteresis Width ◽  
Chip Area

A digital-based Pseudo-differential Schmitt trigger is proposed in this paper which is suitable for ultra-low voltages and pure digital integrated circuit technologies. The proposed Schmitt trigger is implemented according to the design procedure of an analog Schmitt trigger and only using digital CMOS inverters. It is composed of a differential comparator consisting of two CMOS inverters and a cross-coupled inverter pair positive feedback which has simultaneously two outputs of noninverting and inverting. The proposed circuit is the only digital Schmitt trigger which operates in differential mode and its hysteresis center can be changed by the input voltage. Implementing the circuit in digital-based allows the proposed Schmitt trigger to operate in 0.4[Formula: see text]V ultra-low-voltage. Principle operation of the proposed circuit is discussed theoretically and using formulas and its performance is verified by simulation in TSMC 0.18[Formula: see text][Formula: see text]m CMOS process. The proposed circuit occupies only [Formula: see text][Formula: see text][Formula: see text]m2 chip area due to the very low number of transistors. The hysteresis width of the proposed Schmitt trigger is 205[Formula: see text]mV and consumes only 6.64[Formula: see text]nW power.

scholarly journals Low-Voltage Complex Filters Using Current Feedback Operational Amplifiers

2013 ◽  
Vol 2013 ◽  
pp. 1-7 ◽  
Author(s):  
Panagiotis Samiotis ◽  
Costas Psychalinos
Keyword(s):  
Low Voltage ◽  
Operational Amplifiers ◽  
Cmos Process ◽  
Current Feedback ◽  
Mos Transistor ◽  
Low Voltage Operation ◽  
Current Feedback Operational Amplifiers ◽  
Novel Complex ◽  
Simulation Results ◽  
Frequency Behavior

A novel complex filter topology realized using current feedback operational amplifiers as active elements is introduced in this paper. Offered benefits are the low-voltage operation capability and the requirement for employing only grounded passive elements. Two application examples are provided, where the frequency behavior of the derived filters fulfills the ZigBee and Bluetooth standards, respectively. Their performance evaluation has been done through simulation results at postlayout level, using MOS transistor models provided by AMS C35B4 CMOS process.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

scholarly journals Design of a Low Voltage Schmitt Trigger in 0.18 um CMOS Process With Tunable Hysteresis

2013 ◽  
Vol 7 (4) ◽  
Author(s):  
Haroon Rashid ◽  
Md. Mamun ◽  
Md. Syedul Amin ◽  
Hafizah Husain
Keyword(s):  
Low Voltage ◽  
Schmitt Trigger ◽  
Cmos Process

scholarly journals Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

VLSI Design ◽  
2002 ◽  
Vol 15 (2) ◽  
pp. 547-553
Author(s):  
S. M. Rezaul Hasan ◽  
Yufridin Wahab
Keyword(s):  
Power Dissipation ◽  
Figure Of Merit ◽  
Low Voltage ◽  
Logic Gates ◽  
Base Layer ◽  
Cmos Process ◽  
Silicon Area ◽  
Dynamic Power ◽  
Analog Cmos ◽  
Power Delay Product

This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

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