Wireless Transceiver for Three-Dimensional Integrated Circuits Using a Ring Oscillator

2019 ◽  
Vol 29 (10) ◽  
pp. 2050161
Author(s):  
Dongwoo Moon ◽  
Milim Lee ◽  
Changhyun Lee ◽  
Joung-Hu Park ◽  
Changkun Park
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Ring Oscillator ◽  
Oxide Semiconductor ◽  
Voltage Multiplier ◽  
Wireless Transceiver ◽  
Pulse Type

In this paper, we propose an oscillation-type transceiver for wireless chip-to-chip communication (WCC). The proposed transceiver is composed of a ring oscillator, coils, inverter-type amplifier, voltage multiplier and comparator. The ring oscillator itself acts as the on–off keying (OOK) modulator. The envelope of the transferred OOK-modulated signal is detected in the voltage multiplier of the receiver. Given that the proposed transceiver uses an OOK-modulated oscillating signal, the noise immunity is improved compared to the typical pulse-type transceiver. To verify the functionality of the proposed transceiver, we design the transceiver using the 180-nm complementary metal-oxide-semiconductor process. From the measured results, we verify that the proposed transceiver recovers the entered digital signal up to a distance of 0.2[Formula: see text]mm between the primary and secondary coils. Additionally, the sensitivity to the bias voltage of the latch is nonexistent by virtue of removing the latch in the proposed transceiver.

scholarly journals Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 243 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Douglas Maskell ◽  
Nikos Mastorakis
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Cmos Technology ◽  
General Purpose ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Cycle

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

Experimental Basis and Design of a New Cochlear Prosthesis System

1987 ◽  
Vol 96 (1_suppl) ◽  
pp. 76-79
Author(s):  
J. Génin ◽  
R. Charachon
Keyword(s):  
Theoretical Model ◽  
Integrated Circuits ◽  
Cochlear Implant ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Technology ◽  
Experimental Basis ◽  
Cochlear Prosthesis

In a multichannel cochlear prosthesis, electrical interactions between electrodes impose severe limitations on dynamic range and selectivity. We present a theoretical model to cope with these limitations. Building a successful cochlear implant requires full custom-integrated circuits. We present the design of such a device, implemented in complementary metal oxide semiconductor technology. The area of the chip is 9 mm2 and it can stimulate 15 cochlear electrodes with current impulses.

Sign in / Sign up

Export Citation Format

Share Document