A Proposed Technique to Improve the Performance of Receiver by Using Linear Gm-C Low-Pass Filter for mmwave Band Applications

Author(s):  
Pritesh Kumar Yadav ◽  
Ankita Verma ◽  
Prasanna Kumar Misra

Deep submicron CMOS technology proves to be suitable for transceiver design at mmwave band frequencies. At the same time, it has been a challenging task to obtain high performance at mmwave frequencies. In this paper, a 28[Formula: see text]GHz low-IF receiver frontend with improved performance by incorporating a proposed linear Gm-C low-pass filter (LPF) is presented using 40[Formula: see text]nm CMOS technology targeting for 5G wireless system. A mathematical expression for the linearity of the proposed filter is derived and compared with the basic filter model. The improved linearity (IIP3 of [Formula: see text][Formula: see text]dBm) of the proposed filter results in the enhancement of linearity and hence the Figure of Merit (FOM) of the receiver with the proposed filter. The receiver attains a conversion gain of 34.6[Formula: see text]dB, a noise figure of 3.1[Formula: see text]dB and IIP3 of [Formula: see text][Formula: see text]dBm. The total current drawn by the receiver is 27.3[Formula: see text]mA at a 1.2[Formula: see text]V power supply. The overall FOM of the receiver with the proposed filter is improved to 0.30 whereas the FOM of the receiver with the basic filter model is 0.13. The area of the receiver is [Formula: see text] whereas the proposed filter occupies [Formula: see text].

Author(s):  
Nam-Jin Oh

This paper proposes three kinds of single stage RF front-end, called quadrature LMVs (QLMVs), by merging LNA, single-balanced mixer, and quadrature voltage-controlled oscillator (VCO) exploiting a series LC (SLC) network. The low intermediate frequency (IF) or baseband signal near dc can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistor-capacitor (RC) low-pass filter (LPF). Using a 65 nm CMOS technology, the proposed QLMVs are designed. Oscillating at around 2.4 GHz band, the proposed QLMVs achieve the phase noise below ‒107 dB/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 30 dB. The double-side band (DSB) noise figure (NF) of the proposed QLMVs is below 10 dB. The QLMVs consume less than 0.51 mW dc power from a 1-V supply.


Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 734
Author(s):  
Karolis Kiela ◽  
Marijan Jurgo ◽  
Vytautas Macaitis ◽  
Romualdas Navickas

This article presents a wideband reconfigurable integrated low-pass filter (LPF) for 5G NR compatible software-defined radio (SDR) solutions. The filter uses Active-RC topology to achieve high linearity performance. Its bandwidth can be tuned from 2.5 MHz to 200 MHz, which corresponds to a tuning ratio of 92.8. The order of the filter can be changed between the 2nd, 4th, or 6th order; it has built-in process, voltage, and temperature (PVT) compensation with a tuning range of ±42%; and power management features for optimization of the filter performance across its entire range of bandwidth tuning. Across its entire order, bandwidth, and power configuration range, the filter achieves in-band input-referred third-order intercept point (IIP3) between 32.7 dBm and 45.8 dBm, spurious free dynamic range (SFDR) between 63.6 dB and 79.5 dB, 1 dB compression point (P1dB) between 9.9 dBm and 14.1 dBm, total harmonic distortion (THD) between −85.6 dB and −64.5 dB, noise figure (NF) between 25.9 dB and 31.8 dB and power dissipation between 1.19 mW and 73.4 mW. The LPF was designed and verified using 65 nm CMOS process; it occupies a 0.429 mm2 area of silicon and uses a 1.2 V supply.


Author(s):  
Herbert A. Simon

In both the GA and GOFAI traditions, invention or design tasks are viewed as instances of problem solving. To invent or design is to describe an object that performs, in a range of environments, some desired function or serves some intended purpose; the process of arriving at the description is a problem-solving process. In problem solving, the desired object is characterized in two different ways. The problem statement or goal statement characterizes it as an object that satisfies certain criteria of structure and/or performance. The problem solution describes in concrete terms an object that satisfies these criteria. The problem statement specifies what needs to be done; the problem solution describes how to do it [9]. This distinction between the desired object and the achieved object, between problem statement and problem solution, is absolutely fundamental to the idea of solving a problem, for it resolves the paradox of Plato's Meno: How do we recognize the solution of a problem unless we already knew it in advance? The simple answer to Plato is that, although the problem statement does not define a solution, it contains the criteria for recognizing a solution, if and when found. Knowing and being able to apply the recognition test is not equivalent to knowing the solution. Being able to determine, for any given electrical circuit, whether it would operate, to a sufficiently good approximation, as a low-pass filter does not imply that one knows a design for a circuit that meets this condition. In asserting that we do not know the solution in advance, we must be careful to state accurately what the problem is. In theorem proving, for example, we may know, to the last detail, the expression we are trying to prove; what we do not know is what proof (what sequence of expressions, each following inferentially from the set of its predecessors) will terminate in the specified one. Wiles knew well the mathematical expression that is Fermat's last theorem; he spent seven years or more finding its proof. In the domain of theorem proving, the proof is the problem solution and the recognition criteria are the tests that determine whether each step in the proof follows from its predecessors and whether the proof terminates in the desired theorem.


2009 ◽  
Vol 18 (07) ◽  
pp. 1287-1308 ◽  
Author(s):  
EMAN A. SOLIMAN ◽  
SOLIMAN A. MAHMOUD

This paper presents different novel CMOS realizations for the differential difference operational floating amplifier (DDOFA). The DDOFA was first introduced in Ref. 1 and was used to realize different analog circuits like integrators, filters and variable gain amplifiers. New CMOS realizations for the DDOFA are introduced in this literature. Furthermore the DDOFA is modified to realize a fully differential current conveyor (FDCC). Novel CMOS realizations of the FDCC are presented. The FDCC is used to realize second-order band pass–low-pass filter. Performance comparisons between the different realizations of the DDOFA and FDCC are given in this literature. PSPICE simulations of the overall proposed circuits are given using 0.25 μm CMOS Technology from TMSC MOSIS model and dual supply voltages of ±1.5 V.


Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1547
Author(s):  
Xiangyu Chen ◽  
Yasuhiro Takahashi

In this paper, a transimpedance amplifier (TIA) based on floating active inductors (FAI) is presented. Compared with conventional TIAs, the proposed TIA has the advantages of a wider bandwidth, lower power dissipation, and smaller chip area. The schematics and characteristics of the FAI circuit are explained. Moreover, the proposed TIA employs the combination of capacitive degeneration, the broadband matching network, and the regulated cascode input stage to enhance the bandwidth and gain. This turns the TIA design into a fifth-order low pass filter with Butterworth response. The TIA is implemented using 0.18 μ m Rohm CMOS technology and consumes only 10.7 mW with a supply voltage of 1.8 V. When used with a 150 fF photodiode capacitance, it exhibits the following characteristics: gain of 41 dB Ω and −3 dB frequency of 10 GHz. This TIA occupies an area of 180 μ m × 118 μ m.


2017 ◽  
Vol 99 (1) ◽  
pp. 497-507 ◽  
Author(s):  
Saeed Roshani ◽  
Alireza Golestanifar ◽  
Amirhossein Ghaderi ◽  
Hesam Siahkamari ◽  
Derek Abbott

2021 ◽  
Author(s):  
Hima Bindu Katikala ◽  
G.Ramana Murthy ◽  
Yatavakilla Amarendra Nath

Abstract The important challenge for the realization of hearing aids is small size, low cost, low power consumption and better performance, etc. Keeping these requirements in view this work concentrates on the VLSI (Very Large Scale Integrated) implementation of analog circuit that mimic the PPSK (Passive Phase Shift Keying) demodulator with low pass filter. This research deals with RF Cochlear implant circuits and their data transmission. A PPSK modulator is used for uplink data transmission in biomedical implants with simultaneous power, data transmission This paper deals about the implementation of PPSK demodulator with related circuits and low pass filter which are used in cochlear implants consumes low power and operates at 14MHz frequency. These circuits are designed using FINFET 20nm technology with 0.4v DC supply voltage. The performance of proposed design over the previous design is operating at low threshold voltage, reduces static leakage currents and often observed greater than 30 times of improvement in speed performance


Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 102
Author(s):  
Noy Citron ◽  
Eldad Holdengreber ◽  
Oz Sorkin ◽  
Shmuel E. Schacham ◽  
Eliyahu Farber

A high-performance S-band down-conversion microstrip mixer, for operation from 77 K to 300 K, is described. The balanced mixer combines a 90 degree hybrid coupler, two Schottky diodes, a band pass filter, and a low pass filter. The coupler phase shift drastically improves noise rejection. The circuit was implemented according to the configuration obtained from extensive simulation results based on electromagnetic analysis. The experimental results agreed well with the simulation results, showing a maximum measured insertion loss of 0.4 dB at 2 GHz. The microstrip mixer can be easily adjusted to different frequency ranges, up to about 50 GHz, through the proper choice of microstrip configuration. This novel S-band cryogenic mixer, implemented without resorting to special components, shows a very high performance at liquid nitrogen temperatures, making this mixer very suitable for high-temperature superconductive applications, such as front-ends.


This paper presents a voltage-mode(VM) tunable multifunction inverse filter configuration employing current differencing buffered amplifiers (CDBA). The presented structure utilizes two CDBAs, two/three capacitors and four/five resistors to realize inverse low pass filter (ILPF), inverse high pass filter (IHPF), inverse band pass filter (IBPF), and inverse band reject filter(IBRF) from the same circuit topology by suitable selection(s) of the branch admittances(s). PSPICE simulations have been performed with 0.18µm TSMC CMOS technology to validate the theory. Some sample experimental results have also been provided using off-the-shelf IC AD844 based CDBA.


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