MODELS TO ESTIMATE PRINTED CIRCUIT BOARD FABRICATION YIELD DURING THE DESIGN STAGE

1999 ◽  
Vol 09 (03) ◽  
pp. 191-202 ◽  
Author(s):  
RONALD E. GIACHETTI
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Design Stage ◽  
Printed Circuit

In-Plane Pre-Stress Analysis for Automotive Airbag Electronic Control Unit’s Printed Circuit Board Transverse Vibration

2018 ◽  
Author(s):  
Guo Xiaochuan
Keyword(s):  
Simulation Model ◽  
Transverse Vibration ◽  
Printed Circuit Board ◽  
Plate Theory ◽  
Circuit Board ◽  
Structural Vibration ◽  
Design Stage ◽  
Electronic Control ◽  
Component Level ◽  
Printed Circuit

For design of automotive airbag electronic control units (AB ECU), it is essential to have a validated and reliable finite element (FE) simulation model in place in order to allow already in an early design stage for the accurate prediction of the ECU’s structural vibration behavior. A “bottom-up” approach which described in the ASME guide for verification and validation (ASME V&V 10-2006) is applied for the validation of the AB ECU simulation model. The AB ECU is decomposed into different assembly level. Single printed circuit board (PCB) is the lowest elementary component level. In the PCB level simulation and validation, the influence of in-plane pre-stress on PCB’s transverse vibration characteristic has been encountered, but it has been found out that the source of the in-plane pre-stress can not be explained by classical beam/plate theory. Analysis and simulation for PCB fixation reveals that the fundamental source of the in-plane pre-stress is structure’s geometric nonlinearity.

An Object-Oriented Knowledge-Based System for Assembly of Printed Circuit Boards

1991 ◽  
Author(s):  
Sisir K. Padhy ◽  
S. N. Dwivedi
Keyword(s):  
Knowledge Base ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Object Oriented ◽  
Circuit Board ◽  
Design Stage ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Knowledge Based System ◽  
Knowledge Based

Abstract In this paper, Printed Circuit Board Assembly Advisor (PCAAD), an object-oriented knowledge-based system is described. The system aims to aid the designer by suggesting design modifications that will lead to a better design for assembly of the Printed Circuit Boards. To account for the new trends in the printed circuit board production, hybrid technology, i.e. combination of both the through-hole mounted technology and surface mounted technology, is taken into consideration in developing the knowledge base. The assembly constraints as well as various limitations of different techniques and processes are considered to formulate the rules and guidelines. Moreover, a hierarchical rule structure has been employed in creating the knowledge base. Smalltalk-80, the object-oriented language and Surface Percept Description Language (SPDL) are used for the creation of knowledge base. The system provides a high-level user interface and reasoning capability to solve complex problems. It is capable of ranking different designs and suggesting design modifications to the designer during the design stage to eliminate assembly problems in the latter phase of board production.

scholarly journals Maximum Radiated Emissions of Printed Circuit Board Using Analytical Methods

2017 ◽  
Vol 7 (6) ◽  
pp. 2919
Author(s):  
Mohd Zarar Mohd Jenu ◽  
Ahmed M. Sayegh ◽  
Syarfa Zahirah Sapuan
Keyword(s):  
Electromagnetic Compatibility ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Unit Cost ◽  
Circuit Board ◽  
Analytical Models ◽  
Design Stage ◽  
Computational Time ◽  
Printed Circuit ◽  
Radiated Emissions

<span>The rapid progress of technology has imposed significant challenges on Printed Circuit Boards (PCB) designers. Once of those challenges is to satisfy the electromagnetic compatibility (EMC) compliance requirements. For that reason, EMC compliance must be considered earlier at the design stage for time and cost savings. Conventionally, full wave simulation is employed to check whether the designed PCB meets EMC standards or not. However, this method is not a suitable option since it requires intensive computational time and thus increasing the unit cost. This paper describes novel analytical models for estimating the radiated emissions (RE) of PCB. These models can be used to help the circuit designer to modify their circuit based on the maximum allowable RE comparing to the relevant EMC-RE standard limit. Although there are many RE sources on PCB, this paper focuses on the significant source of RE on PCB; namely PCB-traces. The trace geometry, termination impedance, dielectric type, etc. can be specified based on the maximum allowable emissions. The proposed models were verified by comparing the results of the proposed models with both simulation and experimental results. Good agreements were obtained between the analytically computed results and simulation/measurement results with accuracy of ±3dB.</span>

scholarly journals Maximum Radiated Emissions of Printed Circuit Board Using Analytical Methods

2019 ◽  
Vol 7 (6) ◽  
pp. 2919
Author(s):  
Mohd Zarar Mohd Jenu ◽  
Ahmed M. Sayegh ◽  
Syarfa Zahirah Sapuan
Keyword(s):  
Electromagnetic Compatibility ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Unit Cost ◽  
Circuit Board ◽  
Analytical Models ◽  
Design Stage ◽  
Computational Time ◽  
Printed Circuit ◽  
Radiated Emissions

<span>The rapid progress of technology has imposed significant challenges on Printed Circuit Boards (PCB) designers. Once of those challenges is to satisfy the electromagnetic compatibility (EMC) compliance requirements. For that reason, EMC compliance must be considered earlier at the design stage for time and cost savings. Conventionally, full wave simulation is employed to check whether the designed PCB meets EMC standards or not. However, this method is not a suitable option since it requires intensive computational time and thus increasing the unit cost. This paper describes novel analytical models for estimating the radiated emissions (RE) of PCB. These models can be used to help the circuit designer to modify their circuit based on the maximum allowable RE comparing to the relevant EMC-RE standard limit. Although there are many RE sources on PCB, this paper focuses on the significant source of RE on PCB; namely PCB-traces. The trace geometry, termination impedance, dielectric type, etc. can be specified based on the maximum allowable emissions. The proposed models were verified by comparing the results of the proposed models with both simulation and experimental results. Good agreements were obtained between the analytically computed results and simulation/measurement results with accuracy of ±3dB.</span>

An Yield Model for Electronics Assembly

2005 ◽  
Author(s):  
N. Gnanasambandam ◽  
M. Munikrishnan ◽  
V. Poyyapakkam ◽  
P. Borgesen ◽  
K. Srihari
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Solder Bump ◽  
Circuit Board ◽  
Design Stage ◽  
Manufacturing Cost ◽  
Electronic Components ◽  
Yield Model ◽  
Printed Circuit ◽  
Pcb Assembly

Managing assembly yield in the Printed Circuit Board (PCB) assembly process is crucial in reducing the overall manufacturing cost of a product. Being faced with electronic components that have high interconnect (pin or solder bump) count, density, and complexity, it is extremely important to streamline the manufacturing losses arising from misplaced or poorly assembled components. In order to achieve this goal, yield models are utilized to anticipate and evaluate problems and their causes. This activity could be potentially implemented at the design stage or at least much before the product reaches the manufacturing floor. This research examines some important factors that affect area array (BGA, CSP, flip chip) assembly yields, taking a two-pronged approach to modeling. Achievable yield is classified into placement and assembly components and is estimated using a simulation model.

Characteristics of Radiated Emission from a Printed Circuit Board with a Slit

2012 ◽  
Vol 132 (6) ◽  
pp. 404-410 ◽  
Author(s):  
Kenichi Nakayama ◽  
Kenichi Kagoshima ◽  
Shigeki Takeda
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
Radiated Emission

Confirming the Signal Integrity in Transmission of Digital Signals on Microstrip Straight Circuits via the Eye Diagrams

2014 ◽  
Vol 5 (1) ◽  
pp. 737-741
Author(s):  
Alejandro Dueñas Jiménez ◽  
Francisco Jiménez Hernández
Keyword(s):  
Integrated Circuits ◽  
Printed Circuit Board ◽  
Signal Integrity ◽  
High Volume ◽  
Information Storage ◽  
Circuit Board ◽  
Electromagnetic Simulation ◽  
Electronic Systems ◽  
Digital Signals ◽  
Printed Circuit

Because of the high volume of processing, transmission, and information storage, electronic systems presently requires faster clock speeds tosynchronizethe integrated circuits. Presently the “speeds” on the connections of a printed circuit board (PCB) are in the order of the GHz. At these frequencies the behavior of the interconnects are more like that of a transmission line, and hence distortion, delay, and phase shift- effects caused by phenomena like cross talk, ringing and over shot are present and may be undesirable for the performance of a circuit or system.Some of these phrases were extracted from the chapter eight of book “2-D Electromagnetic Simulation of Passive Microstrip Circuits” from the corresponding author of this paper.

Root Cause Analysis of a Connector Time-Delayed Fracture

2015 ◽  
Author(s):  
Prabjit Singh ◽  
Ying Yu ◽  
Robert E. Davis
Keyword(s):  
Printed Circuit Board ◽  
Ceramic Substrate ◽  
Circuit Board ◽  
Delayed Fracture ◽  
Ceramic Substrates ◽  
Printed Circuit ◽  
Root Cause ◽  
Chip Carrier ◽  
Electrical Connections ◽  
Grain Boundary Grooves

Abstract A land-grid array connector, electrically connecting an array of plated contact pads on a ceramic substrate chip carrier to plated contact pads on a printed circuit board (PCB), failed in a year after assembly due to time-delayed fracture of multiple C-shaped spring connectors. The land-grid-array connectors analyzed had arrays of connectors consisting of gold on nickel plated Be-Cu C-shaped springs in compression that made electrical connections between the pads on the ceramic substrates and the PCBs. Metallography, fractography and surface analyses revealed the root cause of the C-spring connector fracture to be plating solutions trapped in deep grain boundary grooves etched into the C-spring connectors during the pre-plating cleaning operation. The stress necessary for the stress corrosion cracking mechanism was provided by the C-spring connectors, in the land-grid array, being compressed between the ceramic substrate and the printed circuit board.

Application of Lock-in Thermography on PCB for Fault Localization and Validation of Failure Mechanism Due to External Discrete Component Variation

2010 ◽  
Author(s):  
William Ng ◽  
Kevin Weaver ◽  
Zachary Gemmill ◽  
Herve Deslandes ◽  
Rudolf Schlangen
Keyword(s):  
Failure Mechanism ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Hot Spot ◽  
Circuit Board ◽  
Discrete Component ◽  
Printed Circuit ◽  
Thermal Signature ◽  
Lock In

Abstract This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.

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