scholarly journals An Integrated Circuit for Radio Astronomy Correlators Supporting Large Arrays of Antennas

2016 ◽  
Vol 05 (02) ◽  
pp. 1650002 ◽  
Author(s):  
Larry R. D’Addario ◽  
Douglas Wang
Keyword(s):  
Energy Efficiency ◽  
Power Consumption ◽  
Integrated Circuit ◽  
Cross Correlation ◽  
Silicon On Insulator ◽  
System Level ◽  
Level Energy ◽  
Silicon Area ◽  
Power Efficient ◽  
The Cost

Radio telescopes that employ arrays of many antennas are in operation, and ever larger ones are being designed and proposed. Signals from the antennas are combined by cross-correlation. While the cost of most components of the telescope is proportional to the number of antennas N, the cost and power consumption of cross-correlation are proportional to [Formula: see text] and dominate at sufficiently large N. Here, we report the design of an integrated circuit (IC) that performs digital cross-correlations for arbitrarily many antennas in a power-efficient way. It uses an intrinsically low-power architecture in which the movement of data between devices is minimized. In a large system, each IC performs correlations for all pairs of antennas but for a portion of the telescope’s bandwidth (the so-called “FX” structure). In our design, the correlations are performed in an array of 4096 complex multiply-accumulate (CMAC) units. This is sufficient to perform all correlations in parallel for 64 signals (N[Formula: see text]=[Formula: see text]32 antennas with two opposite-polarization signals per antenna). When N is larger, the input data are buffered in an on-chip memory and the CMACs are reused as many times as needed to compute all correlations. The design has been synthesized and simulated so as to obtain accurate estimates of the ICs size and power consumption. It is intended for fabrication in a 32[Formula: see text]nm silicon-on-insulator process, where it will require less than 12[Formula: see text]mm2 of silicon area and achieve an energy efficiency of 1.76–3.3[Formula: see text]pJ per CMAC operation, depending on the number of antennas. Operation has been analyzed in detail up to [Formula: see text]. The system-level energy efficiency, including board-level I/O, power supplies, and controls, is expected to be 5–7[Formula: see text]pJ per CMAC operation. Existing correlators for the JVLA ([Formula: see text]) and ALMA ([Formula: see text]) telescopes achieve about 5000[Formula: see text]pJ and 1000[Formula: see text]pJ, respectively using application-specific ICs (ASICs) in older technologies. To our knowledge, the largest-N existing correlator is LEDA at [Formula: see text]; it uses GPUs built in 28[Formula: see text]nm technology and achieves about 1000[Formula: see text]pJ. Correlators being designed for the SKA telescopes ([Formula: see text] and [Formula: see text]) using FPGAs in 16[Formula: see text]nm technology are predicted to achieve about 100[Formula: see text]pJ.

scholarly journals A New ALU Design using PNS-FCR: Static CMOS Logic for Microprocessors

2019 ◽  
Vol 8 (6S2) ◽  
pp. 876-882
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Design Methodology ◽  
Total Power ◽  
Data Path ◽  
Power Efficient ◽  
Efficient Data ◽  
Main Component ◽  
Static Logic ◽  
Important Design

Arithmetic Logic Unit (ALU) is the main component in the processors. Most important design consideration in integrated circuit is power. In all the components of ALU data path is the active one and it consumes more percent of power in the total power. In the modern microprocessors it is important to have power efficient data paths. To reduce the power consumption in microprocessors the ALU is designed using PNS-FCR static CMOS logic. In this paper static CMOS logic is used to reduce power consumption. Static technique does not need any clock. So it leads to less power consumption. For the implementation of the ALU with the PNS-FCR static logic mentor graphics tool is used. The power consumption of ALU is compared with and without using FCR. An 8-bit ALU is designed in mentor graphics with 130nm technology. The proposed design methodology gives less power consumption

scholarly journals Power Efficient, Low Noise 2-5 GHz Phase Locked Loop

2011 ◽  
Vol 16 (4) ◽  
pp. 66-72
Author(s):  
V.Sh. Melikyan ◽  
A.A. Durgaryan ◽  
H.P. Petrosyan ◽  
A.G. Stepanyan
Keyword(s):  
Power Consumption ◽  
Efficient Solution ◽  
Phase Locked Loop ◽  
Low Noise ◽  
System Level ◽  
Voltage Controlled Oscillator ◽  
Power Efficient ◽  
Area Overhead ◽  
Output Noise ◽  
5 Ghz

A power and noise efficient solution for phase locked loop (PLL) is presented. A lock detector is implemented to deactivate the PLL components, except the voltage controlled oscillator (VCO), in the locked state. Signals deactivating/activating the PLL are discussed on system level. The introduced technique significantly saves power and decreases PLL output jitter. As a result whole PLL power consumption and output noise decreased about 35-38% in expense of approximately 17% area overhead

scholarly journals Energy-Efficient Ternary Multipliers Using CNT Transistors

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 643
Author(s):  
Sepehr Tabrizchi ◽  
Atiyeh Panahi ◽  
Fazel Sharifi ◽  
Hamid Mahmoodi ◽  
Abdel-Hameed A. Badawy
Keyword(s):  
Energy Consumption ◽  
Integrated Circuits ◽  
Power Consumption ◽  
Integrated Circuit ◽  
Field Effect Transistors ◽  
Approximate Computing ◽  
Digital Signals ◽  
Acceptable Error ◽  
Power Efficient ◽  
Multiple Valued Logic

In recent decades, power consumption has become an essential factor in attracting the attention of integrated circuit (IC) designers. Multiple-valued logic (MVL) and approximate computing are some techniques that could be applied to integrated circuits to make power-efficient systems. By utilizing MVL-based circuits instead of binary logic, the information conveyed by digital signals increases, and this reduces the required interconnections and power consumption. On the other hand, approximate computing is a class of arithmetic computing used in systems where the accuracy of the computation can be traded-off for lower energy consumption. In this paper, we propose novel designs for exact and inexact ternary multipliers based on carbon-nanotube field-effect transistors (CNFETs). The unique characteristics of CNFETs make them a desirable alternative to MOSFETs. The simulations are conducted using Synopsys HSPICE. The proposed design is compared against existing ternary multipliers. The results show that the proposed exact multiplier reduces the energy consumption by up to 6 times, while the best inexact design improves energy efficiency by up to 35 time compared to the latest state-of-the-art methods. Using the imprecise multipliers for image processing provides evidence that these proposed designs are a low-power system with an acceptable error.

Assessing System-Level Energy Efficiency of mmWave-Based Wearable Networks

2016 ◽  
Vol 34 (4) ◽  
pp. 923-937 ◽  
Author(s):  
Olga Galinina ◽  
Alexander Pyattaev ◽  
Kerstin Johnsson ◽  
Andrey Turlikov ◽  
Sergey Andreev ◽  
...  
Keyword(s):  
Energy Efficiency ◽  
System Level ◽  
Level Energy

scholarly journals Power-efficient beam tracking during connected mode DRX in mmWave and sub-THz systems

2020 ◽  
Author(s):  
Syed Hashim Ali Shah ◽  
Sundar Aditya ◽  
Sundeep Rangan
Keyword(s):  
Power Consumption ◽  
Power Saving ◽  
Cellular Systems ◽  
System Level ◽  
Maximum Throughput ◽  
Throughput Performance ◽  
Digital Beamforming ◽  
Power Efficient ◽  
Reduce Power Consumption ◽  
Discontinuous Reception

Discontinuous reception (DRX), wherein a user equipment (UE) temporarily disables its receiver, is a critical power saving feature in modern cellular systems. DRX is likely to be aggressively used at mmWave and sub-THz frequencies due to the high front-end power consumption. A key challenge for DRX at these frequencies is blockage-induced link outages: A UE will likely need to track many directional links to ensure reliable multi-connectivity, thereby increasing the power consumption. In this paper, we explore reinforcement learning-based link tracking policies in connected mode DRX that reduce power consumption by tracking only a fraction of the available links, but without adversely affecting the outage and throughput performance. Through detailed, system level simulations at 28 GHz (5G) and 140 GHz (6G), we observe that even sub-optimal link tracking policies can achieve considerable power savings with relatively little degradation in outage and throughput performance, especially with digital beamforming at the UE. In particular, we show that it is feasible to reduce power consumption by 75% and still achieve up to 95% (80%) of the maximum throughput using digital beamforming at 28 GHz (140 GHz), subject to an outage probability of at most 1%.

scholarly journals A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

2021 ◽  
Author(s):  
Daniel Junehee Lee
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Cmos Technology ◽  
Sar Adc ◽  
Least Significant Bit ◽  
Silicon Area ◽  
Analog To Digital ◽  
Power Efficient ◽  
Successive Approximation Register ◽  
Simulation Results

file:///C:/Users/MWF/Downloads/Lee, Daniel Junehee.The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.

CNTFET-Based Ternary Logic Gates

2020 ◽  
pp. 72-92
Author(s):  
Suman Rani ◽  
Balwinder Singh
Keyword(s):  
Energy Efficiency ◽  
Comparative Analysis ◽  
Power Consumption ◽  
Integrated Circuit ◽  
Logic Gates ◽  
Cmos Technology ◽  
Nand Gate ◽  
Ternary Logic ◽  
Average Delay ◽  
Universal Gates

In the recent digital designs, there are certain circumstances where energy efficiency and ease is required, and in such situations, ternary logic (or three-valued logic) is favored. Ternary logic is an auspicious supernumerary to the conventional binary (0, 1) logic design techniques as this one is possible to attain straightforwardness and energy efficiency. This chapter deals with the comparative analysis of CMOS and CNTFET-based ternary inverter and universal gates design. The simulation result is analyzed and validated with a Hailey simulation program with integrated circuit (HSPICE) simulations. The average delay and power consumption in CNTFET-based ternary inverter have been reduced by approximately 90.3% and 48.8% respectively, as compared to CMOS-based ternary inverter design. Likewise, delay is reduced by 50% and power gets 99% reduction in ternary CNTFET NAND gate as compared to CMOS-based ternary NAND gat. It is concluded that CNFETs are faster and consume less power compared to CMOS technology.

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