scholarly journals Energy-Efficient Ternary Multipliers Using CNT Transistors

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 643
Author(s):  
Sepehr Tabrizchi ◽  
Atiyeh Panahi ◽  
Fazel Sharifi ◽  
Hamid Mahmoodi ◽  
Abdel-Hameed A. Badawy
Keyword(s):  
Energy Consumption ◽  
Integrated Circuits ◽  
Power Consumption ◽  
Integrated Circuit ◽  
Field Effect Transistors ◽  
Approximate Computing ◽  
Digital Signals ◽  
Acceptable Error ◽  
Power Efficient ◽  
Multiple Valued Logic

In recent decades, power consumption has become an essential factor in attracting the attention of integrated circuit (IC) designers. Multiple-valued logic (MVL) and approximate computing are some techniques that could be applied to integrated circuits to make power-efficient systems. By utilizing MVL-based circuits instead of binary logic, the information conveyed by digital signals increases, and this reduces the required interconnections and power consumption. On the other hand, approximate computing is a class of arithmetic computing used in systems where the accuracy of the computation can be traded-off for lower energy consumption. In this paper, we propose novel designs for exact and inexact ternary multipliers based on carbon-nanotube field-effect transistors (CNFETs). The unique characteristics of CNFETs make them a desirable alternative to MOSFETs. The simulations are conducted using Synopsys HSPICE. The proposed design is compared against existing ternary multipliers. The results show that the proposed exact multiplier reduces the energy consumption by up to 6 times, while the best inexact design improves energy efficiency by up to 35 time compared to the latest state-of-the-art methods. Using the imprecise multipliers for image processing provides evidence that these proposed designs are a low-power system with an acceptable error.

scholarly journals A New ALU Design using PNS-FCR: Static CMOS Logic for Microprocessors

2019 ◽  
Vol 8 (6S2) ◽  
pp. 876-882
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Design Methodology ◽  
Total Power ◽  
Data Path ◽  
Power Efficient ◽  
Efficient Data ◽  
Main Component ◽  
Static Logic ◽  
Important Design

Arithmetic Logic Unit (ALU) is the main component in the processors. Most important design consideration in integrated circuit is power. In all the components of ALU data path is the active one and it consumes more percent of power in the total power. In the modern microprocessors it is important to have power efficient data paths. To reduce the power consumption in microprocessors the ALU is designed using PNS-FCR static CMOS logic. In this paper static CMOS logic is used to reduce power consumption. Static technique does not need any clock. So it leads to less power consumption. For the implementation of the ALU with the PNS-FCR static logic mentor graphics tool is used. The power consumption of ALU is compared with and without using FCR. An 8-bit ALU is designed in mentor graphics with 130nm technology. The proposed design methodology gives less power consumption

Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application

2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Logic Synthesis ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Timing Models ◽  
High Temperature Operation

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

scholarly journals Lithography for enabling advances in integrated circuits and devices

2012 ◽  
Vol 370 (1973) ◽  
pp. 4015-4041 ◽  
Author(s):  
C. Michael Garner
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Extreme Ultraviolet ◽  
Field Effect Transistors ◽  
Semiconductor Industry ◽  
High Volume ◽  
Pattern Transfer ◽  
Time Pattern ◽  
Technology Roadmap ◽  
The Future

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

scholarly journals Ultra-Low Power and High-Throughput SRAM Design to Enhance AI Computing Ability in Autonomous Vehicles

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 256
Author(s):  
Youngbae Kim ◽  
Shreyash Patel ◽  
Heekyung Kim ◽  
Nandakishor Yadav ◽  
Kyuwon Ken Choi
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
Low Power ◽  
High Throughput ◽  
Autonomous Vehicles ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
Electrical Performance ◽  
Large Area ◽  
Ultra Low Power

Power consumption and data processing speed of integrated circuits (ICs) is an increasing concern in many emerging Artificial Intelligence (AI) applications, such as autonomous vehicles and Internet of Things (IoT). Existing state-of-the-art SRAM architectures for AI computing are highly accurate and can provide high throughput. However, these SRAMs have problems that they consume high power and occupy a large area to accommodate complex AI models. A carbon nanotube field-effect transistors (CNFET) device has been reported as a potential candidates for AI devices requiring ultra-low power and high-throughput due to their satisfactory carrier mobility and symmetrical, good subthreshold electrical performance. Based on the CNFET and FinFET device’s electrical performance, we propose novel ultra-low power and high-throughput 8T SRAMs to circumvent the power and the throughput issues in Artificial Intelligent (AI) computation for autonomous vehicles. We propose two types of novel 8T SRAMs, P-Latch N-Access (PLNA) 8T SRAM structure and single-ended (SE) 8T SRAM structure, and compare the performance with existing state-of-the-art 8T SRAM architectures in terms of power consumption and speed. In the SRAM circuits of the FinFET and CNFET, higher tube and fin numbers lead to higher operating speed. However, the large number of tubes and fins can lead to larger area and more power consumption. Therefore, we optimize the area by reducing the number of tubes and fins without compromising the memory circuit speed and power. Most importantly, the decoupled reading and writing of our new SRAMs cell offers better low-power operation due to the stacking of device in the reading part, as well as achieving better readability and writability, while offering read Static Noise Margin (SNM) free because of isolated reading path, writing path, and greater pull up ratio. In addition, the proposed 8T SRAMs show even better performance in delay and power when we combine them with the collaborated voltage sense amplifier and independent read component. The proposed PLNA 8T SRAM can save 96%, while the proposed SE 8T SRAM saves around 99% in writing power consumption compared with the existing state-of-the-art 8T SRAM in FinFET model, as well as 99% for writing operation in CNFET model.

scholarly journals Power Efficient Clock Distribuition for Switched Capacitor DC-DC Converters

2018 ◽  
Vol 10 (1) ◽  
pp. 27
Author(s):  
A. S. R. Murthy ◽  
Sridhar T.
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
Power Distribution ◽  
High Speed ◽  
Low Voltage ◽  
Data Communication ◽  
Distribution Networks ◽  
Propagation Delay ◽  
Switched Capacitor ◽  
Power Efficient

<p>In various VLSI based digital systems, on-chip interconnects have become the system bottleneck in state-of-the-art chips, limiting the performance of high-speed clock distributions and data communication devices in terms of propagation delay and power consumption. Increasing power requirements and power distribution to multi-core architectures is also posing a challenge to power distribution networks in the integrated circuits. Clock distribution networks for the switched capacitor converters becomes a non-trivial task and the increased interconnect lengths cause clock degradation and power dissipation. Therefore, this paper introduce low swing signaling schemes to decrease delay and power consumption. A comparative study presented of low voltage signaling schemes in terms of delay, power consumption and power delay product. Here, we have presented a power efficient signaling topology for driving the clocks to higher interconnect lengths.</p>

scholarly journals Performance Efficient Alu using Finfet

2019 ◽  
Vol 8 (4) ◽  
pp. 11449-11455
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Power Analysis ◽  
High Speed ◽  
Power Saving ◽  
Arithmetic Functions ◽  
Power Efficient ◽  
Logical Unit ◽  
Simulation Results ◽  
Logical Functions

According to the prophecy of Moore, the concentration of transistors in an integrated circuit doubles every two years. But this is limited by the technologies used in the fabrication of integrated circuits, as the systems are scaled down. FinFET technology aims to combat this challenge. The construction of power efficient high speed Arithmetic & Logical Unit (ALU) using FinFET technology is proposed in this paper. Proposed FinFET based ALU is designed with arithmetic functions like high speed addition, multiplication and logical functions such as AND and XOR. Simulation results of the proposed power efficient high speed FinFET ALU proves to be better with a power saving of 80.5%. FinFET has the advantage of providing low power without compromising on the Performance. The power analysis for ALU is done using CADENCE-VIRTUOSO, which is known for its accuracy.

scholarly journals Selection of MOSFET Sizes by Fuzzy Sets Intersection in the Feasible Solutions Space

2012 ◽  
Vol 10 (3) ◽  
Author(s):  
S. Polanco-Martagón ◽  
G. Reyes-Salgado ◽  
G. Flores-Becerra ◽  
E. Tlelo-Cuautle ◽  
L.G. De la Fraga ◽  
...  
Keyword(s):  
Power Consumption ◽  
Fuzzy Sets ◽  
Analog Circuits ◽  
Integrated Circuit ◽  
Field Effect Transistors ◽  
Current Feedback ◽  
Minimum Power Consumption ◽  
High Bandwidth ◽  
Feasible Solutions ◽  
Current Feedback Operational Amplifier

A fuzzy sets intersection procedure to select the optimum sizes of analog circuits composed of metal-oxidesemiconductor field-effect-transistors (MOSFETs), is presented. The cases of study are voltage followers (VFs) and a current-feedback operational amplifier (CFOA), where the width (W) and length (L) of the MOSFETs are selected from the space of feasible solutions computed by swarm or evolutionary algorithms. The evaluation of three objectives, namely: gain, bandwidth and power consumption; is performed using HSPICETM with standard integrated circuit (IC) technology of 0.35μm for the VFs and 180nm for the CFOA. Therefore, the intersection procedure among three fuzzy sets representing “gain close to unity”, ”high bandwidth” and “minimum power consumption”, is presented. The main advantage relies on its usefulness to select feasible W/L sizes automatically but by considering deviation percentages from the desired target specifications. Basically, assigning a threshold to each fuzzy set does it. As a result, the proposed approach selects the best feasible sizes solutions to guarantee and to enhance the performances of the ICs in analog signal processing applications.

Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 °C

2008 ◽  
Vol 1069 ◽  
Author(s):  
Philip Neudeck ◽  
David J. Spry ◽  
Liang-Yu Chen ◽  
Carl W. Chang ◽  
Glenn M. Beheim ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect Transistors ◽  
Aircraft Engines ◽  
Electrical Parameters ◽  
Air Atmosphere ◽  
Circuit Technology ◽  
Very High

ABSTRACTNASA has been developing very high temperature semiconductor integrated circuits for use in the hot sections of aircraft engines and for Venus exploration. This paper reports on long-term 500 °C electrical operation of prototype 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). As of this writing, some devices have surpassed 4000 hours of continuous 500 °C electrical operation in oxidizing air atmosphere with minimal change in relevant electrical parameters.

scholarly journals An Artificial Neutral Network Chip Based on Two-Dimensional Semiconductor

2020 ◽  
Author(s):  
Shunli Ma ◽  
Tianxiang Wu ◽  
Xinyu Chen ◽  
Yin Wang ◽  
Hongwei Tang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Large Scale ◽  
Field Effect Transistors ◽  
Recognition Rate ◽  
Activation Function ◽  
Machine Learning Algorithms ◽  
Two Dimensional ◽  
Wafer Scale ◽  
Large Current

Abstract Two-dimensional semiconductors can be used to build integrated circuits for running artificial neural networks (ANN) with higher energy efficiency. The implementation of an ANN with 2D semiconductors has been held back by the large-scale and high-quality transistors required for running machine learning algorithms. Here we demonstrate the first functional MoS2 analog ANN integrated circuit, including memory, multiply-and-accumulate (MAC), activation function, and weight update circuits. The ANN integrated circuit is realized through 818 field effect transistors (FETs) with wafer-scale and high-homogeneity MoS2 film. The large current on/off ratio and output linearity of these MoS2 FETs allow the realization of convolutional and activation function circuits with a few number of transistors. This ANN can be used for recognizing tactile digit, showing the recognition rate exceeding 97%. Our work demonstrates wafer-scale processing of a 2D semiconductor for building integrated circuits with the functions of AI computation.

scholarly journals An Integrated Circuit for Radio Astronomy Correlators Supporting Large Arrays of Antennas

2016 ◽  
Vol 05 (02) ◽  
pp. 1650002 ◽  
Author(s):  
Larry R. D’Addario ◽  
Douglas Wang
Keyword(s):  
Energy Efficiency ◽  
Power Consumption ◽  
Integrated Circuit ◽  
Cross Correlation ◽  
Silicon On Insulator ◽  
System Level ◽  
Level Energy ◽  
Silicon Area ◽  
Power Efficient ◽  
The Cost

Radio telescopes that employ arrays of many antennas are in operation, and ever larger ones are being designed and proposed. Signals from the antennas are combined by cross-correlation. While the cost of most components of the telescope is proportional to the number of antennas N, the cost and power consumption of cross-correlation are proportional to [Formula: see text] and dominate at sufficiently large N. Here, we report the design of an integrated circuit (IC) that performs digital cross-correlations for arbitrarily many antennas in a power-efficient way. It uses an intrinsically low-power architecture in which the movement of data between devices is minimized. In a large system, each IC performs correlations for all pairs of antennas but for a portion of the telescope’s bandwidth (the so-called “FX” structure). In our design, the correlations are performed in an array of 4096 complex multiply-accumulate (CMAC) units. This is sufficient to perform all correlations in parallel for 64 signals (N[Formula: see text]=[Formula: see text]32 antennas with two opposite-polarization signals per antenna). When N is larger, the input data are buffered in an on-chip memory and the CMACs are reused as many times as needed to compute all correlations. The design has been synthesized and simulated so as to obtain accurate estimates of the ICs size and power consumption. It is intended for fabrication in a 32[Formula: see text]nm silicon-on-insulator process, where it will require less than 12[Formula: see text]mm2 of silicon area and achieve an energy efficiency of 1.76–3.3[Formula: see text]pJ per CMAC operation, depending on the number of antennas. Operation has been analyzed in detail up to [Formula: see text]. The system-level energy efficiency, including board-level I/O, power supplies, and controls, is expected to be 5–7[Formula: see text]pJ per CMAC operation. Existing correlators for the JVLA ([Formula: see text]) and ALMA ([Formula: see text]) telescopes achieve about 5000[Formula: see text]pJ and 1000[Formula: see text]pJ, respectively using application-specific ICs (ASICs) in older technologies. To our knowledge, the largest-N existing correlator is LEDA at [Formula: see text]; it uses GPUs built in 28[Formula: see text]nm technology and achieves about 1000[Formula: see text]pJ. Correlators being designed for the SKA telescopes ([Formula: see text] and [Formula: see text]) using FPGAs in 16[Formula: see text]nm technology are predicted to achieve about 100[Formula: see text]pJ.

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