Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm

2021 ◽  
Vol 17 (3) ◽  
pp. 1-16
Author(s):  
Eros Camacho-Ruiz ◽  
Santiago Sánchez-Solano ◽  
Piedad Brox ◽  
Macarena C. Martínez-Rodríguez
Keyword(s):  
Secure Communication ◽  
Electronic Devices ◽  
Information Leakage ◽  
Quantum Computers ◽  
Programming Environment ◽  
Polynomial Multiplication ◽  
Cryptographic Algorithms ◽  
Speed Up ◽  
Good Trade ◽  
On Chip

Post-quantum cryptographic algorithms have emerged to secure communication channels between electronic devices faced with the advent of quantum computers. The performance of post-quantum cryptographic algorithms on embedded systems has to be evaluated to achieve a good trade-off between required resources (area) and timing. This work presents two optimized implementations to speed up the NTRUEncrypt algorithm on a system-on-chip. The strategy is based on accelerating the most time-consuming operation that is the truncated polynomial multiplication. Hardware dedicated modules for multiplication are designed by exploiting the presence of consecutive zeros in the coefficients of the blinding polynomial. The results are validated on a PYNQ-Z2 platform that includes a Zynq-7000 SoC from Xilinx and supports a Python-based programming environment. The optimized version that exploits the presence of double, triple, and quadruple consecutive zeros offers the best performance in timing, in addition to considerably reducing the possibility of an information leakage against an eventual attack on the device, making it practically negligible.

scholarly journals Double Security using Dynamic S-Box inside Aes Algorithm

2019 ◽  
Vol 8 (6) ◽  
pp. 1893-1898
Keyword(s):  
Secure Communication ◽  
Electronic Devices ◽  
Quantum Computers ◽  
Brute Force ◽  
Substitution Box ◽  
Avalanche Effect ◽  
Data Message ◽  
A New Technique ◽  
And Storage ◽  
Day By Day

Now a days internet and other electronic devices have become an non removable part of our society. Day by day we are increasing the usage of data for transmission and storage as well. But there is always a problem for our data to be in wrong hands or hacked by someone. In order to ensure our secrecy of data we use bunch of algorithms to secure it. These algorithms comes under the vast section of cryptology, which means an art of hiding the data to make it secure. But as we all know when there is a hacker he would find every possible way to bypass the security algorithms. Some of the attacks are very popular in cryptology like Brute Force Attacks which checks each possible key combination to hack the data message. Due to the arrival of quantum computers in upcoming future hacking time will be decreased about a factor of around 1000 times. Now the best possible solution for enciphering data is Advanced Encryption Standard .This algorithm consists of two basic things static Substitution Box (S-Box) and other register operation. In this paper we have introduced a new technique to ensure a secure communication by using a dynamic S-Box with avalanche value of 58.59% as well as we also improved the overall area, delay (1.227 ns) and optimized the power to possible extents. Our results also approached above the traditional AES security as our modification improves avalanche effect also

Multiprocessor transport surveillance video system based on "system on chip" technology

2020 ◽  
Author(s):  
Ш.С. Фахми ◽  
Н.В. Шаталова ◽  
В.В. Вислогузов ◽  
Е.В. Костикова
Keyword(s):  
System On Chip ◽  
Reference Points ◽  
Surveillance Video ◽  
Video Information ◽  
Chip Technology ◽  
Intelligent Video Surveillance System ◽  
Speed Up ◽  
Algorithmic Analysis ◽  
Computational Procedures ◽  
On Chip

В данной работе предлагаются математический аппарат и архитектура многопроцессорной транспортной системы на кристалле (МПТСнК). Выполнена программно-аппаратная реализация интеллектуальной системы видеонаблюдения на базе технологии «система на кристалле» и с использованием аппаратного ускорителя известного метода формирования опорных векторов. Архитектура включает в себя сложно-функциональные блоки анализа видеоинформации на базе параллельных алгоритмов нахождения опорных точек изображений и множества элементарных процессоров для выполнения сложных вычислительных процедур алгоритмов анализа с использованием средств проектирования на базе реконфигурируемой системы на кристалле, позволяющей оценить количество аппаратных ресурсов. Предлагаемая архитектура МПТСнК позволяет ускорить обработку и анализ видеоинформации при решении задач обнаружения и распознавания чрезвычайных ситуаций и подозрительных поведений. In this paper, we propose the mathematical apparatus and architecture of a multiprocessor transport system on a chip (MPTSoC). Software and hardware implementation of an intelligent video surveillance system based on the "system on chip" technology and using a hardware accelerator of the well-known method of forming reference vectors. The architecture includes complex functional blocks for analyzing video information based on parallel algorithms for finding image reference points and a set of elementary processors for performing complex computational procedures for algorithmic analysis. using design tools based on a reconfigurable system on chip that allows you to estimate the amount of hardware resources. The proposed MPTSoC architecture makes it possible to speed up the processing and analysis of video information when solving problems of detecting and recognizing emergencies and suspicious behaviors

scholarly journals Practical Security of RSA Against NTC-Architecture Quantum Computing Attacks

2021 ◽  
Author(s):  
Kai Li ◽  
Qing-yu Cai
Keyword(s):  
Quantum Computing ◽  
Ion Trap ◽  
Quantum Algorithms ◽  
Coherence Time ◽  
Quantum Computers ◽  
Quantum Time ◽  
Speed Up ◽  
Key Length ◽  
Concurrent Architecture ◽  
Qubit Gate

AbstractQuantum algorithms can greatly speed up computation in solving some classical problems, while the computational power of quantum computers should also be restricted by laws of physics. Due to quantum time-energy uncertainty relation, there is a lower limit of the evolution time for a given quantum operation, and therefore the time complexity must be considered when the number of serial quantum operations is particularly large. When the key length is about at the level of KB (encryption and decryption can be completed in a few minutes by using standard programs), it will take at least 50-100 years for NTC (Neighbor-only, Two-qubit gate, Concurrent) architecture ion-trap quantum computers to execute Shor’s algorithm. For NTC architecture superconducting quantum computers with a code distance 27 for error-correcting, when the key length increased to 16 KB, the cracking time will also increase to 100 years that far exceeds the coherence time. This shows the robustness of the updated RSA against practical quantum computing attacks.

scholarly journals Drone Secure Communication Protocol for Future Sensitive Applications in Military Zone

Sensors ◽  
2021 ◽  
Vol 21 (6) ◽  
pp. 2057
Author(s):  
Yongho Ko ◽  
Jiyoon Kim ◽  
Daniel Gerbi Duguma ◽  
Philip Virgil Astillo ◽  
Ilsun You ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
Secure Communication ◽  
Communication Protocol ◽  
Denial Of Service ◽  
Mutual Authentication ◽  
Information Leakage ◽  
Security Protocol ◽  
Security Requirements ◽  
Forward Secrecy ◽  
Perfect Forward Secrecy

Unmanned Aerial Vehicle (UAV) plays a paramount role in various fields, such as military, aerospace, reconnaissance, agriculture, and many more. The development and implementation of these devices have become vital in terms of usability and reachability. Unfortunately, as they become widespread and their demand grows, they are becoming more and more vulnerable to several security attacks, including, but not limited to, jamming, information leakage, and spoofing. In order to cope with such attacks and security threats, a proper design of robust security protocols is indispensable. Although several pieces of research have been carried out with this regard, there are still research gaps, particularly concerning UAV-to-UAV secure communication, support for perfect forward secrecy, and provision of non-repudiation. Especially in a military scenario, it is essential to solve these gaps. In this paper, we studied the security prerequisites of the UAV communication protocol, specifically in the military setting. More importantly, a security protocol (with two sub-protocols), that serves in securing the communication between UAVs, and between a UAV and a Ground Control Station, is proposed. This protocol, apart from the common security requirements, achieves perfect forward secrecy and non-repudiation, which are essential to a secure military communication. The proposed protocol is formally and thoroughly verified by using the BAN-logic (Burrow-Abadi-Needham logic) and Scyther tool, followed by performance evaluation and implementation of the protocol on a real UAV. From the security and performance evaluation, it is indicated that the proposed protocol is superior compared to other related protocols while meeting confidentiality, integrity, mutual authentication, non-repudiation, perfect forward secrecy, perfect backward secrecy, response to DoS (Denial of Service) attacks, man-in-the-middle protection, and D2D (Drone-to-Drone) security.

scholarly journals Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

2022 ◽  
Vol 15 (2) ◽  
pp. 1-33
Author(s):  
Mikhail Asiatici ◽  
Paolo Ienne
Keyword(s):  
Large Scale ◽  
Sparse Matrix ◽  
Memory Systems ◽  
Graph Analytics ◽  
Matrix Vector Multiplication ◽  
Area Reduction ◽  
Cache Line ◽  
Speed Up ◽  
Memory Accesses ◽  
On Chip

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by requesting each cache line only once, even when there are multiple misses corresponding to it. However, such reuse mechanism is traditionally implemented using an associative lookup. This limits the number of misses that are considered for reuse to a few tens, at most. In this article, we present an efficient pipeline that can process and store thousands of outstanding misses in cuckoo hash tables in on-chip SRAM with minimal stalls. This brings the same bandwidth advantage as a larger cache for a fraction of the area budget, because outstanding misses do not need a data array, which can significantly speed up irregular memory-bound latency-insensitive applications. In addition, we extend nonblocking caches to generate variable-length bursts to memory, which increases the bandwidth delivered by DRAMs and their controllers. The resulting miss-optimized memory system provides up to 25% speedup with 24× area reduction on 15 large sparse matrix-vector multiplication benchmarks evaluated on an embedded and a datacenter FPGA system.

scholarly journals Direct Ink Writing of Materials for Electronics-Related Applications: A Mini Review

2021 ◽  
Vol 8 ◽  
Author(s):  
Zhenzhong Hou ◽  
Hai Lu ◽  
Ying Li ◽  
Laixia Yang ◽  
Yang Gao
Keyword(s):  
Human Life ◽  
Electronic Devices ◽  
Electronic Components ◽  
Direct Ink Writing ◽  
Recent Developments ◽  
Print Materials ◽  
On Chip ◽  
Functional Components ◽  
Printing Techniques

Recently, the fabrication of electronics-related components via direct ink writing (DIW) has attracted much attention. Compared to the conventionally fabricated electronic components, DIW-printed ones have more complicated structures, higher accuracy, improved efficiency, and even enhanced performances that arise from well-designed architectures. The DIW technology allows directly print materials on a variety of flat substrates, even a conformal one, well suiting them to applications such as wearable devices and on-chip integrations. Here, recent developments in DIW printing of emerging components for electronics-related applications are briefly reviewed, including electrodes, electronic circuits, and functional components. The printing techniques, processes, ink materials, advantages, and properties of DIW-printed architectures are discussed. Finally, the challenges and outlooks on the manufacture of 3D structured electronic devices by DIW are outlined, pointing out future designs and developments of DIW technology for electronics-related applications. The combination of DIW and electronic devices will help to improve the quality of human life and promote the development of science and society.

Quantum blockchain system

2021 ◽  
pp. 2150343
Author(s):  
Xiao-Jun Wen ◽  
Yong-Zhi Chen ◽  
Xin-Can Fan ◽  
Zheng-Zhong Yi ◽  
Zoe L. Jiang ◽  
...  
Keyword(s):  
Quantum Teleportation ◽  
Secure Communication ◽  
Quantum Computers ◽  
Computing Power ◽  
Broad Application ◽  
Digital Currency ◽  
Blockchain Technology ◽  
Quantum Secure Communication ◽  
Complexity Problem ◽  
Application Prospects

Blockchain technology represented by Bitcoin and Ethereum has been deeply developed and widely used due to its broad application prospects such as digital currency and IoT. However, the security of the existing blockchain technologies built on the classical cryptography depends on the computational complexity problem. With the enhancement of the attackers’ computing power, especially the upcoming quantum computers, this kind of security is seriously threatened. Based on quantum hash, quantum SWAP test and quantum teleportation, a quantum blockchain system is proposed with quantum secure communication. In classical cryptographic theory sense, the security of this system is unconditional since it has nothing to do with the attackers’ computing power and computing resources.

Sustainability of Public Key Cryptosystem in Quantum Computing Paradigm

2018 ◽  
pp. 563-588
Author(s):  
Krishna Asawa ◽  
Akanksha Bhardwaj
Keyword(s):  
Quantum Computing ◽  
Secure Communication ◽  
Prime Numbers ◽  
Cryptographic Protocols ◽  
Public Key ◽  
Quantum Computers ◽  
New Paradigm ◽  
Public Key Cryptosystems ◽  
Computing Paradigm ◽  
Diffie Hellman

With the emergence of technological revolution to host services over Internet, secure communication over World Wide Web becomes critical. Cryptographic protocols are being in practice to secure the data transmission over network. Researchers use complex mathematical problem, number theory, prime numbers etc. to develop such cryptographic protocols. RSA and Diffie Hellman public key crypto systems have proven to be secure due to the difficulty of factoring the product of two large primes or computing discrete logarithms respectively. With the advent of quantum computers a new paradigm shift on public key cryptography may be on horizon. Since superposition of the qubits and entanglement behavior exhibited by quantum computers could hold the potential to render most modern encryption useless. The aim of this chapter is to analyze the implications of quantum computing power on current public key cryptosystems and to show how these cryptosystems can be restructured to sustain in the new computing paradigm.

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