scholarly journals Power Consumption Models for Decimation FIR Filters in Multistandard Receivers

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-15 ◽  
Author(s):  
Khaled Grati ◽  
Nadia Khouja ◽  
Bertrand Le Gal ◽  
Adel Ghazel
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Fir Filter ◽  
Fir Filters ◽  
Computation Complexity ◽  
Decimation Filters ◽  
Direct Form ◽  
Decimation Filter ◽  
Multistandard Receiver ◽  
The Impact

Decimation filters are widely used in communication-embedded systems. In fact, decimation filters are useful for implementing channel filtering or selection with low-computation complexity requirements. Many multistandard receiver designs that are required in ubiquitous embedded systems are based on a cascade of decimation filter processing. Filter number and implementation architectures have a significant impact on system performances, such as computation complexity, area, throughput, and power consumption. In this work, we present filter power consumption estimation models for FIR filters. Power consumption models were obtained from a large number of FIR filter syntheses using a direct form. Several curves that estimate power consumption were extracted from these synthesis results. Then, we have evaluated the impact of polyphase decomposition on power consumption of FIR filter and compared it with the direct form results. Some tips regarding power consumption were deduced for the polyphase implementation form. The aim of this work is to help a system designer to select an efficient implementation for FIR in terms of power consumption without having to implement and synthesize the different possible solutions. The proposed method is applied for STMicroelectronics libraries 90 nm and 65 nm low power then validated with a use case of multistandard receiver designing.

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

scholarly journals Modeling the Power Consumption of Function-Level Code Relocation for Low-Power Embedded Systems

2019 ◽  
Vol 9 (11) ◽  
pp. 2354 ◽  
Author(s):  
Hayeon Choi ◽  
Youngkyoung Koo ◽  
Sangsoo Park
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Flash Memory ◽  
Power Reduction ◽  
Battery Life ◽  
Actual System ◽  
Proposed Model ◽  
Assembly Instructions ◽  
Static Ram ◽  
The Impact

The problems associated with the battery life of embedded systems were addressed by focusing on memory components that are heterogeneous and are known to meaningfully affect the power consumption and have not been fully exploited thus far. Our study establishes a model that predicts and orders the efficiency of function-level code relocation. This is based on extensive code profiling that was performed on an actual system to discover the impact and was achieved by using function-level code relocation between the different types of memory, i.e., flash memory and static RAM, to reduce the power consumption. This was accomplished by grouping the assembly instructions to evaluate the distinctive power reduction efficiency depending on function code placement. As a result of the profiling, the efficiency of the function-level code relocation was the lowest at 11.517% for the branch and control groups and the highest at 12.623% for the data processing group. Further, we propose a prior relocation-scoring model to estimate the effective relocation order among functions in a program. To demonstrate the effectiveness of the proposed model, benchmarks in the MiBench benchmark suite were selected as case studies. The experimental results are consistent in terms of the scored outputs produced by the proposed model and measured power reduction efficiencies.

scholarly journals A High-Performance FIR filter Architecture for Reconfigurable Applications

2019 ◽  
pp. 420-424
Author(s):  
R. Yerriswamy ◽  
D. Vishnu Vardhan ◽  
Sankar Lal Sharma
Keyword(s):  
High Performance ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Flow Diagram ◽  
Fir Filters ◽  
Significant Saving ◽  
Project Analysis ◽  
Complex Design ◽  
Direct Form ◽  
Filter Architecture

Transpose form finite-impulse response (FIR) filters are characteristically pipelined and support multiple constant multiplications (MCM) procedure that results in significant saving of calculation. However, transpose form configuration does not specifically support the block performing not like direct-form configuration. In this paper, we investigate the possibility of realization of block FIR filter in transpose shape configuration for area-delay efficient realization of huge order FIR filters for both fixed applications. Based on a detailed computational investigation of transpose form configuration of FIR filter, we have derived a flow diagram for transpose shape block FIR filter with reduced register complexity. A detailed block formulation is detailed for transpose form FIR filter. We have inferred a general multiplier-based architecture for the proposed transpose form block filter for reconfigurable applications. A reduced-complex design using multiple constant multiplications scheme is also showed for block implementation of fixed FIR filters. The proposed architecture obtains less area, less delay and less power consumption compared with the existing architecture of direct form structure for medium or long filter lengths. For this project analysis for determining area, power and delay it uses Xilinx.

Estimating OLED Display Device Lifetime from pixel and screen brightness and its application

2019 ◽  
Vol 2019 (1) ◽  
pp. 331-338 ◽  
Author(s):  
Jérémie Gerhardt ◽  
Michael E. Miller ◽  
Hyunjin Yoo ◽  
Tara Akhavan
Keyword(s):  
Image Processing ◽  
Power Consumption ◽  
Model Parameters ◽  
Display Device ◽  
Image Processing Algorithm ◽  
Pixel Value ◽  
Device Lifetime ◽  
The Impact ◽  
Oled Display

In this paper we discuss a model to estimate the power consumption and lifetime (LT) of an OLED display based on its pixel value and the brightness setting of the screen (scbr). This model is used to illustrate the effect of OLED aging on display color characteristics. Model parameters are based on power consumption measurement of a given display for a number of pixel and scbr combinations. OLED LT is often given for the most stressful display operating situation, i.e. white image at maximum scbr, but having the ability to predict the LT for other configurations can be meaningful to estimate the impact and quality of new image processing algorithms. After explaining our model we present a use case to illustrate how we use it to evaluate the impact of an image processing algorithm for brightness adaptation.

On the Impact of Heat Pumps Electric Load on the Power Consumption of Lampedusa

2020 ◽  
Author(s):  
Marina Bonomolo ◽  
Mariano Giuseppe Ippolito ◽  
Giuliana Leone ◽  
Rossano Musca ◽  
Vincenzo Porgi ◽  
...  
Keyword(s):  
Power Consumption ◽  
Heat Pumps ◽  
Electric Load ◽  
The Impact

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals Efficient Prediction of Network Traffic for Real-Time Applications

2019 ◽  
Vol 2019 ◽  
pp. 1-11 ◽  
Author(s):  
Muhammad Faisal Iqbal ◽  
Muhammad Zahid ◽  
Durdana Habib ◽  
Lizy Kurian John
Keyword(s):  
Power Consumption ◽  
Real Time ◽  
Power Management ◽  
Dynamic Resource Allocation ◽  
Computation Complexity ◽  
Real Time Traffic ◽  
Double Exponential ◽  
Efficient Prediction ◽  
Dynamic Resource ◽  
Double Exponential Smoothing

Accurate real-time traffic prediction is required in many networking applications like dynamic resource allocation and power management. This paper explores a number of predictors and searches for a predictor which has high accuracy and low computation complexity and power consumption. Many predictors from three different classes, including classic time series, artificial neural networks, and wavelet transform-based predictors, are compared. These predictors are evaluated using real network traces. Comparison of accuracy and cost, both in terms of computation complexity and power consumption, is presented. It is observed that a double exponential smoothing predictor provides a reasonable tradeoff between performance and cost overhead.

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