scholarly journals Classic and Quantum Capacitances in Bernal Bilayer and Trilayer Graphene Field Effect Transistor

2013 ◽  
Vol 2013 ◽  
pp. 1-7 ◽  
Author(s):  
Hatef Sadeghi ◽  
Daniel T. H. Lai ◽  
Jean-Michel Redoute ◽  
Aladin Zayegh
Keyword(s):  
Metal Oxide ◽  
Electric Fields ◽  
Bilayer Graphene ◽  
Oxide Semiconductor ◽  
Analytical Models ◽  
Quantum Capacitance ◽  
Graphene Field Effect Transistor ◽  
Similar Temperature ◽  
Bernal Stacking ◽  
Trilayer Graphene

Our focus in this study is on characterizing the capacitance voltage (C-V) behavior of Bernal stacking bilayer graphene (BG) and trilayer graphene (TG) as the channel of FET devices. The analytical models of quantum capacitance (QC) of BG and TG are presented. Although QC is smaller than the classic capacitance in conventional devices, its contribution to the total metal oxide semiconductor capacitor in graphene-based FET devices becomes significant in the nanoscale. Our calculation shows that QC increases with gate voltage in both BG and TG and decreases with temperature with some fluctuations. However, in bilayer graphene the fluctuation is higher due to its tunable band structure with external electric fields. In similar temperature and size, QC in metal oxide BG is higher than metal oxide TG configuration. Moreover, in both BG and TG, total capacitance is more affected by classic capacitance as the distance between gate electrode and channel increases. However, QC is more dominant when the channel becomes thinner into the nanoscale, and therefore we mostly deal with quantum capacitance in top gate in contrast with bottom gate that the classic capacitance is dominant.

Mathematical Modeling of Junctionless Triple Material Double Gate MOSFET for Low Power Applications

2019 ◽  
Vol 56 ◽  
pp. 71-79 ◽  
Author(s):  
S. Darwin ◽  
T.S. Arun Samuel
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Analytical Models ◽  
Approximation Technique ◽  
Double Gate ◽  
Effect Transistor

This paper describes the analytical modeling and simulation of Triple Material Double Gate Metal Oxide Semiconductor Field Effect Transistor (TMDG MOSFET) with no junctions. Three kind of gate materials with different work function values over the channel helps to improve the ON current and to form a barrier in the channel helps to reduce OFF current. It has been found from the obtained results that the OFF current or leakage current of the device is exactly low (IOFF =10-11 A) which is fit for low power applications. Also, the extracted value of ION current (10-3 A) has proved that there is a remarkable improvement with decreasing device dimensions. The overall gate length (L), work functions of gate materials, oxide thickness (tox), silicon thickness (tsi) and doping concentration (Nd) are optimized at 60nm, 4.8eV, 4.6eV, 4.4eV, 1nm, 10nm and 1019 cm-3 respectively. The 2-D Poisson equation has been solved by using parabolic approximation technique to obtain the potential distribution function in the channel. Based on this expression, analytical models of the lateral electric field, subthreshold slope and drain current for Junctionless Triple Material Double Gate Metal oxide semiconductor Field Effect Transistor (JL TMDG MOSFET) were derived. Finally, the validity of the proposed analytical model is compared with numerical solution simulation data results which are obtained by using TCAD device simulator.

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

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