scholarly journals Development of Low-Noise Small-Area 24 GHz CMOS Radar Sensor

2016 ◽  
Vol 2016 ◽  
pp. 1-12
Author(s):  
Min Yoon ◽  
Jee-Youl Ryu
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Small Area ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Radar Sensor ◽  
Low Power Dissipation ◽  
Chip Size ◽  
24 Ghz

We present a low-noise small-area 24 GHz CMOS radar sensor for automotive collision avoidance. This sensor is based on direct-conversion pulsed-radar architecture. The proposed circuit is implemented using TSMC 0.13 μm RF (radio frequency) CMOS (fT/fmax=120/140 GHz) technology, and it is powered by a 1.5 V supply. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF are used to reduce parasitic capacitance at the band of 24 GHz. The proposed sensor has low cost and low power dissipation since it is realized using CMOS process. The proposed sensor showed the lowest noise figure of 2.9 dB and the highest conversion gain of 40.2 dB as compared to recently reported research results. It also showed small chip size of 0.56 mm2, low power dissipation of 39.5 mW, and wide operating temperature range of −40 to +125°C.

scholarly journals A 65 nm Duplex Transconductance Path Up-Conversion Mixer for 24 GHz Automotive Short-Range Radar Sensor Applications

Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 594
Author(s):  
Tahesin Samira Delwar ◽  
Abrar Siddique ◽  
Manas Ranjan Biswal ◽  
Prangyadarsini Behera ◽  
Yeji Choi ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Short Range ◽  
Noise Figure ◽  
Supply Voltage ◽  
Common Source ◽  
Cmos Process ◽  
Radar Sensor ◽  
Sensor Applications ◽  
The Common ◽  
24 Ghz

A 24 GHz highly-linear upconversion mixer, based on a duplex transconductance path (DTP), is proposed for automotive short-range radar sensor applications using the 65-nm CMOS process. A mixer with an enhanced transconductance stage consisting of a DTP is presented to improve linearity. The main transconductance path (MTP) of the DTP includes a common source (CS) amplifier, while the secondary transconductance path (STP) of the DTP is implemented as an improved cross-quad transconductor (ICQT). Two inductors with a bypass capacitor are connected at the common nodes of the transconductance stage and switching stage of the mixer, which acts as a resonator and helps to improve the gain and isolation of the designed mixer. According to the measured results, at 24 GHz the proposed mixer shows that the linearity of output 1-dB compression point (OP1dB) is 3.9 dBm. And the input 1-dB compression point (IP1dB) is 0.9 dBm. Moreover, a maximum conversion gain (CG) of 2.49 dB and a noise figure (NF) of 3.9 dB is achieved in the designed mixer. When the supply voltage is 1.2 V, the power dissipation of the mixer is 3.24 mW. The mixer chip occupies an area of 0.42 mm2.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

2021 ◽  
Vol 18 (4) ◽  
pp. 1327-1330
Author(s):  
S. Manjula ◽  
R. Karthikeyan ◽  
S. Karthick ◽  
N. Logesh ◽  
M. Logeshkumar
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Design System ◽  
Cmos Process ◽  
Design Specifications ◽  
Noise Amplifier

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

Low-power CMOS LNA based on dual resistive-feedback structure with peaking inductor for wideband application

2013 ◽  
Vol 5 (1) ◽  
pp. 65-70 ◽  
Author(s):  
Meng-Ting Hsu ◽  
Shih-Yu Hsu ◽  
Yu-Hwa Lin
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Output Stage ◽  
Chip Area ◽  
Inductive Peaking ◽  
Resistive Feedback ◽  
Low Power Cmos ◽  
Noise Amplifier

This paper presents a low-power and low-noise amplifier (LNA) with resistive-feedback configuration. The design consists of two resistive-feedback amplifiers. In order to reduce the chip area, a resistive-feedback inverter is adopted for input matching. The output stage adopts basic topology of an RC feedback for output matching, and adds two inductors for inductive peaking at the high band. The implemented LNA has a peak gain of 10.5 dB, the input reflection coefficient S11 is lower than −8 dB and the output reflection S22 is lower than −10.8 dB, and noise figure of 4.2–5.2 dB is between 1 and 10 GHz while consuming 12.65 mW from a 1.5 V supply. The chip area is only 0.69 mm2 and the figure of merit is 6.64 including the area estimation. The circuit was fabricated in a TSMC 0.18 um CMOS process.

scholarly journals 24 GHz low-power switch-channel CMOS transceiver for wireless localization

2014 ◽  
Vol 7 (6) ◽  
pp. 615-622
Author(s):  
Tao Zhang ◽  
Amin Hamidian ◽  
Ran Shu ◽  
Viswanathan Subramanian
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Continuous Wave ◽  
Noise Figure ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Power Circuit ◽  
Chip Area ◽  
Switch Channel ◽  
24 Ghz

A 24 GHz low-power transceiver is designed, fabricated, and characterized using 130 nm complementary metal-oxide semiconductor (CMOS) process. The designed transceiver is targeted for frequency-modulated-continuous-wave (FMCW) wireless local positioning. The transceiver includes four switchable receiving channels, one transmitting channel and local-oscillator generation circuitries. Several power-saving techniques are implemented, such as switch channel and adaptive mixer biasing. The design aspects of the low-power circuit blocks and integration considerations are presented in details. The integrated transceiver has a chip area of only 2.2 mm × 1.7 mm. In transmitting mode the transceiver achieves an output power of 4 dBm and phase noise of −90 dBc/Hz at 1 MHz, while consuming 75 mW power consumption under 1.5 V power supply. In switch-channel receiving mode the transceiver demonstrates 31 dB gain and 6 dB noise figure with 65 mW power consumption. The transceiver measurements compare well with the simulated results and achieve state-of-the-art performance with very low-power consumption.

PULSED LOW POWER CMOS

1994 ◽  
Vol 05 (02) ◽  
pp. 159-177 ◽  
Author(s):  
THAD GABARA
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Signal Propagation ◽  
Capacitive Coupling ◽  
Cmos Process ◽  
Cmos Circuit ◽  
Static State ◽  
Low Power Dissipation ◽  
Power Capability ◽  
Circuit Technique

A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS. In addition, several advantages occur in this new circuit technique: (1) low power signal propagation through several gates in series can occur during each evaluation cycle; (2) crowbar current does not occur; (3) additional placed devices, i.e. bipolar, diodes, JFETs are not required to generate this low power capability; (4) the Conventional CMOS process is used to fabricate the circuit; (5) the same physical layout can be used either as a PPS CMOS circuit or as a Conventional CMOS circuit; (6) the device count is the same as that of Conventional CMOS; (7) PPS CMOS uses quasistatic logic levels; (8) capacitive coupling is used to store and restore the contents of a memory cell; (9) the parasitic diodes of the MOS devices are used to improve the noise margin of the circuit; (10) PPS CMOS can easily hold a static state and have the same low power dissipation properties of data inactive Conventional CMOS.

scholarly journals Research and Design of X-band Low Noise Amplifier Based on CMOS Process

2021 ◽  
Vol 2108 (1) ◽  
pp. 012102
Author(s):  
Chao Ma ◽  
Hongjiang Wu ◽  
Xudong Lu ◽  
Haitao Sun
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Center Frequency ◽  
Cmos Process ◽  
Actual Measurement ◽  
Chip Area ◽  
Chip Size ◽  
Noise Amplifier ◽  
Stage Matching

Abstract Based on CMOS process, a low noise amplifier(LNA) operating at 7.4GHz~11.4GHz was designed. The two-stage differential cascode structure is adopted. Transformer was used to achieve inter-stage matching. Balun was used to achieve input and output matching, which reduces the number of inductors used, effectively reduces the chip size while ensuring good gain and noise figure. The actual measurement results show that the power gain at the center frequency of 9.4GHz is 27dB, the maximum noise figure is less than 3.82dB, the output power 1dB compression point is greater than 8dBm, the chip area is only 0.41mm×0.83mm(excluding PAD).

scholarly journals 0.5-7.5 GHZ LOW-POWER, INDUCTORLESS CURRENT FOLDED MIXER IN 0.18-μM CMOS FOR BROADBAND APPLICATIONS

2013 ◽  
pp. 112-116
Author(s):  
ZAHRA GHANE FASHTALI ◽  
MAHROKH MAGHSOODI ◽  
REZA EBRAHIMI ATANI ◽  
MEHRGAN MAHDAVI
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Noise Figure ◽  
Cmos Process ◽  
Conversion Gain ◽  
Fully Differential ◽  
Dc Power ◽  
Maximum Conversion ◽  
Cell Topology ◽  
Down Conversion

A fully differential low-power down-conversion mixer using a TSMC 0.18-μm CMOS process is presented in this paper. The proposed mixer is based on a folded double-balanced Gilbert cell topology that enhances conversion gain and reduces power dissipation. Though, this mixer is designed for 5.8 GHz ISM band applications, but at 0.5-7.5 GHz, the proposed mixer exhibits a maximum conversion gain of 12dB, maximum IIP3 of -2.5 dBm, maximum input 1-dB compression point of -13 dBm, the minimum DSB noise figure of 9.2 dB and a dc power consumption of 2.52 mW at 1.8 V power supply. Also, this circuit architecture increases port-to-port isolations to above 140 dB. Moreover this mixer is suitable for broadband applications.

Characterization of lateral bipolar transistor structures

1990 ◽  
Vol 48 (4) ◽  
pp. 628-629
Author(s):  
N. David Theodore ◽  
Sophie Verdonckt-Vandebroek ◽  
C. Barry Carter ◽  
S. Simon Wong
Keyword(s):  
Low Power ◽  
Cross Sections ◽  
Power Dissipation ◽  
Diagnostic Techniques ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Structural Defects ◽  
Low Power Dissipation ◽  
Packing Densities ◽  
Driving Capability

Semiconductor devices are being scaled down into the submicron regime in order to meet technological demands for increased device-packing densities. Other factors considered for device design include low power dissipation, noise immunity, speed and high driving capability. Of these factors, high packing densities and low power dissipation can be derived using Coinplementary-Metal-Oxide-Semiconductor (CMOS) schemes. Bipolar-Junction-Transistor (BJT) schemes on the other hand provide driving capability, low noise performance and speed, at the expense however of greater device power- consumption. Combining CMOS and BJT technologies, a compromise can be struck between devicespeed and power dissipation. Most such combinations have resulted in vertical BJT requiring complex fabrication sequences. Recently, simpler lateral BJTs have been proposed for use in Bipolar CMOS processes. The viability of such semiconducting devices depends in part on the absence or controlled presence of structural defects. Diagnostic techniques are therefore required that are capable of high spatial resolution, for investigating the origin, behavior and possible elimination of fabrication-process-induced defects. Transmission electron microscopy (TEM) of device cross-sections can be effectively used for this purpose. In this study, lateral BJT structures are characterized using cross-section TEM and the results are correlated with electrical device-behavior.

A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology

2017 ◽  
Vol 26 (09) ◽  
pp. 1750134 ◽  
Author(s):  
Jun-Da Chen ◽  
Song-Hao Wang
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Conversion Gain ◽  
Dc Power ◽  
Down Conversion

The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

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