scholarly journals Delta-sigma ADC modulator for multibit data converters using passive adder entrenched second order noise shaping

2021 ◽  
Vol 10 (4) ◽  
pp. 1952-1959
Author(s):  
Ali Kareem Nahar ◽  
Hussain K. Khleaf
Keyword(s):  
Harmonic Distortion ◽  
Data Converters ◽  
Second Order ◽  
Quantization Noise ◽  
Weighted Averaging ◽  
Noise Shaping ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Fully Differential ◽  
Delta Sigma

This paper introduces a multi-bit data converters (MDC) modulator of the 2nd order delta-sigma analog-to-digital converter use the passive adder proposed. The noise shaping quantizer can provide feedback that has generated quantization noise and perform additional shaping noise first-order by coupling noise method.Thus, two Integrator's with ring amplifier and the MDC is shaped by noise coupling quantizer know the 2nd-order noise coupled with somewhat of a DAC modulator. At a summing point, the inputs are summed and then filtered with a low pass filter. A cyclic second order response is generated with a data weighted averaging (DWA) technique in which the DACs ' outputs are limited to one of two states in the noise shaping responses. Mainly as a result of the harmonic distortion in circuits of amplifier. Transistor rate is equipped for the fully differential switched condenser integrator used, a comparator and DWA. The modulator with proposed DWA design, almost quarterly improved timing margin. A simulated SNDR of 92dB is obtained at 20 MHz sampling frequency; while a sinusoidal output of 4.112 dBFS is tested at 90µs besides 20 MHz as the bandwidth. The power consumption is 0.33 mW while the voltage of the supply is 1.2V.

scholarly journals Second order noise shaping for data-weighted averaging technique to improve sigma-delta DAC performance

2021 ◽  
Vol 10 (1) ◽  
pp. 79
Author(s):  
Ali Kerem Nahar ◽  
Ansam Subhi Jaddar ◽  
Hussain K. Khleaf ◽  
Mohmmed Jawad Mortada Mobarek
Keyword(s):  
Power Dissipation ◽  
Second Order ◽  
Weighted Averaging ◽  
Noise Shaping ◽  
Sigma Delta ◽  
Averaging Technique ◽  
Delta Sigma ◽  
Low Levels ◽  
Digital To Analog ◽  
Data Weighted Averaging

<p>In general, the noise shaping responses, a cyclic second order response is delivered by the method of data weighted averaging (DWA) in which the output of the digital-to-analog convertor (DAC) is restricted to one of two states. DWA works efficiently for rather low levels of quantizing; it begins presenting considerable difficulties when internal levels of quantizing are extended further. Though, each added bit of internal quantizing causes an exponentially increasing in power dissipation, complexity and size of the DWA logic and the DAC. This gives a controlled seconnd order response accounting for the mismatch of the elements of DAC. The multi-bit DAC is made up of numerous single-bit DACs having values thereof chosen via a digital encoder. This research presents a discussion of the influence of mismatching between unit elements of the Delta-Sigma DAC. This results in a constrained second order response accounting for mismatch of DAC elements. The results of the simulation showed how the effectiveness of DWA method is in reducing band tones. Furthermore, DWA method has proved its efficiency in solving the mismatching of DAC unit elements. The noise of the mismatching elements is enhanced 11 dB at 0.01 with the proposed DWA, thereby enhancing the efficiency of the DAC in comparison to the efficiency of the DAC with no use of the circuit of DWA</p>

scholarly journals Wideband Reconfigurable Integrated Low-Pass Filter for 5G Compatible Software Defined Radio Solutions

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 734
Author(s):  
Karolis Kiela ◽  
Marijan Jurgo ◽  
Vytautas Macaitis ◽  
Romualdas Navickas
Keyword(s):  
Software Defined Radio ◽  
Dynamic Range ◽  
Noise Figure ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Filter Performance ◽  
Low Pass ◽  
Bandwidth Tuning

This article presents a wideband reconfigurable integrated low-pass filter (LPF) for 5G NR compatible software-defined radio (SDR) solutions. The filter uses Active-RC topology to achieve high linearity performance. Its bandwidth can be tuned from 2.5 MHz to 200 MHz, which corresponds to a tuning ratio of 92.8. The order of the filter can be changed between the 2nd, 4th, or 6th order; it has built-in process, voltage, and temperature (PVT) compensation with a tuning range of ±42%; and power management features for optimization of the filter performance across its entire range of bandwidth tuning. Across its entire order, bandwidth, and power configuration range, the filter achieves in-band input-referred third-order intercept point (IIP3) between 32.7 dBm and 45.8 dBm, spurious free dynamic range (SFDR) between 63.6 dB and 79.5 dB, 1 dB compression point (P1dB) between 9.9 dBm and 14.1 dBm, total harmonic distortion (THD) between −85.6 dB and −64.5 dB, noise figure (NF) between 25.9 dB and 31.8 dB and power dissipation between 1.19 mW and 73.4 mW. The LPF was designed and verified using 65 nm CMOS process; it occupies a 0.429 mm2 area of silicon and uses a 1.2 V supply.

scholarly journals A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6456
Author(s):  
Fernando Cardes ◽  
Nikhita Baladari ◽  
Jihyun Lee ◽  
Andreas Hierlemann
Keyword(s):  
Low Power ◽  
Low Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
Second Order ◽  
Frequency Noise ◽  
Voltage Controlled Oscillator ◽  
Noise Shaping ◽  
Delta Sigma Modulator ◽  
Delta Sigma

This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.

THE DIFFERENTIAL DIFFERENCE OPERATIONAL FLOATING AMPLIFIER: NEW CMOS REALIZATIONS AND APPLICATIONS

2009 ◽  
Vol 18 (07) ◽  
pp. 1287-1308 ◽  
Author(s):  
EMAN A. SOLIMAN ◽  
SOLIMAN A. MAHMOUD
Keyword(s):  
Analog Circuits ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Variable Gain Amplifiers ◽  
Variable Gain ◽  
Fully Differential ◽  
Filter Performance ◽  
Low Pass ◽  
Band Pass

This paper presents different novel CMOS realizations for the differential difference operational floating amplifier (DDOFA). The DDOFA was first introduced in Ref. 1 and was used to realize different analog circuits like integrators, filters and variable gain amplifiers. New CMOS realizations for the DDOFA are introduced in this literature. Furthermore the DDOFA is modified to realize a fully differential current conveyor (FDCC). Novel CMOS realizations of the FDCC are presented. The FDCC is used to realize second-order band pass–low-pass filter. Performance comparisons between the different realizations of the DDOFA and FDCC are given in this literature. PSPICE simulations of the overall proposed circuits are given using 0.25 μm CMOS Technology from TMSC MOSIS model and dual supply voltages of ±1.5 V.

Single Phase Inverter System using Proportional Resonant Current Control

2017 ◽  
Vol 8 (4) ◽  
pp. 1913
Author(s):  
K.C. Chen ◽  
S. Salimin ◽  
S. A. Zulkifli ◽  
R. Aziz
Keyword(s):  
Single Phase ◽  
Harmonic Distortion ◽  
Harmonic Spectrum ◽  
Current Control ◽  
Nonlinear Load ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Phase Inverter ◽  
Current Controller ◽  
Single Phase Inverter

<span>This paper presents the harmonic reduction performance of proportional resonant (PR) current controller in single phase inverter system connected to nonlinear load. In the study, proportional resonant current controller and low pass filter is discussed to eliminate low order harmonics injection in single phase inverter system. The potential of nonlinear load in producing harmonics is showed and identified by developing a nonlinear load model using a full bridge rectifier circuit. The modelling and simulation is done in MATLAB Simulink while harmonic spectrum results are obtained using Fast Fourier Transfor. End result show PR current controller capability to overcome the injection of current harmonic problems thus improved the overall total harmonic distortion (THD).</span>

Study of a second order low pass filter based on hybrid SETMOS

2013 ◽  
Author(s):  
Li Cai ◽  
Qiang Kang ◽  
Dang Yuan Shi
Keyword(s):  
Second Order ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass

The Design of Ideal Positioning Servo System

2015 ◽  
Vol 816 ◽  
pp. 132-139
Author(s):  
Ľubica Miková ◽  
Alexander Gmiterko ◽  
Michal Kelemen
Keyword(s):  
Frequency Characteristic ◽  
Pid Controller ◽  
Transfer Functions ◽  
Servo System ◽  
Second Order ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass ◽  
Degree Of Stability

The paper deals with the design of an ideal positioning servo system. To achieve this aim, we will derive transfer functions of the PID controller and the second-order low-pass filter while using typical fault frequencies for PID controller with a low pass filter. Consequently, an overall frequency characteristic of the open servo system will be depicted. This characteristic will be further used to determine the amplitude and phase safety, which determine the degree of stability system.

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