scholarly journals Design and simulate a doherty power amplifier using GaAs technology for telecommunication applications

2019 ◽  
Vol 15 (2) ◽  
pp. 845
Author(s):  
Ehsan Barmala
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Power Amplifiers ◽  
High Efficiency ◽  
Maximum Output Power ◽  
Input Power ◽  
Power Divider ◽  
Maximum Efficiency ◽  
Maximum Output ◽  
Doherty Power Amplifier

<span>In this paper, a Doherty power amplifier was designed and simulated at 2.4 GHz central frequency which has high efficiency. A Doherty power amplifier is a way to increase the efficiency in the power amplifiers. OMMIC ED02AH technology and PHEMT transistors, which is made of gallium arsenide, have been used in this simulation. The Doherty power amplifier unique feature is its simple structure which is consisting of two parallel power amplifiers and transmission lines. In order to integrate the circuit, the Doherty power transmission amplifier lines were implemented using an inductor and capacitive components. Also, the Wilkinson power divider is used on the chip input. To improve the efficiency, the auxiliary amplifier dimensions is selected enlarge and the further input power is allocated it by the power divider. A parallel R-C circuit has been used at the input of transistors to improve their stability. Simulation results show that the Doherty power amplifier has 17.2 dB output power gain, 23 dBm maximum output power, and its output power P<sub>1dB</sub> =22.6dBm at compression point -1 dB, also, its maximum efficiency is 55.5%.</span>

scholarly journals Extended Bandwidth and Increased Efficiency Quasi-Doherty Power Amplifier Design With A Revised Approach For Load Modulation

2021 ◽  
Author(s):  
Seyedehmarzieh Rouhani ◽  
Kasra Rouhi ◽  
Adib Abrishamifar ◽  
Majid Tayarani
Keyword(s):  
Power Amplifier ◽  
High Power ◽  
Maximum Output Power ◽  
Input Power ◽  
Maximum Efficiency ◽  
Maximum Output ◽  
Power Added Efficiency ◽  
Active Feedback ◽  
Doherty Power Amplifier ◽  
Load Modulation

This paper presents an approach to power added efficiency (PAE) increase for Quasi-Doherty power amplifier (Q-DPA) design. For this aim, active feedback is utilized instead of a passive quarter wavelength transmission line (TL) usage, which is conventionally used in the DPA schematic. PAE increase can be done by applying an accurate load modulation to the main amplifier (PAmain), especially for technologies in which output impedance of the main power amplifier (Zout,main) considerably varies in both low and high power regions. Because such precise modulation is still based on a modified TL, this approach suffers from the inherent narrowband behavior of that TL. As a consequence, expecting a wideband DPA may not be satisfied in all cases. To deal with this issue, active feedback is used to play a role in reaching PAmain, which is not saturated before, to its maximum efficiency at the highest level of received input power (Pin) in the high power region. Following Zout,main trajectories in power and frequency sweeps simultaneously just by a passive TL are not needed anymore. Still, for the sake of preventing total PAE degradation due to the consummated power by the feedback path’s power amplifier (PAfeedback) should be limited, analytical confinement is provided in this work. A comparison is made between GaAs pHEMT 0.25um MMIC technology-based conventional DPA and the proposed revised approach based-DPA to verify the mentioned approach. The proposed PA shows maximum output power of 33.4 dBm, maximum PAE of 41.6, fractional bandwidth of 11%. The Q-DPA works with a maximum power gain of 24.16.

scholarly journals Increased Efficiency of a Current Compensating Load Modulation Based MMIC Doherty Power Amplifier Design In 0.25m GaAs pHEMT Technology

2020 ◽  
Author(s):  
Seyedehmarzieh Rouhani ◽  
Kasra Rouhi ◽  
Adib Abrishamifar ◽  
Majid Tayarani
Keyword(s):  
Power Amplifier ◽  
Second Harmonic ◽  
Maximum Output Power ◽  
Input Power ◽  
Maximum Output ◽  
Modulation Equation ◽  
Gain Compression ◽  
Power Added Efficiency ◽  
Doherty Power Amplifier ◽  
Load Modulation

In this work, a premise is applied to the conventional load modulation equation of Doherty power amplifier (DPA) in 0.25 m GaAs pHEMT technology to compensate output impedance of main amplifier ( Z out,main ) variation, even in low power region. Using this modified modulation leads to the DPAs power added efficiency (PAE) increase in comparison by the case in which the load modulation revision is ignored, which is also designed in this paper. Second harmonic rejection networks are also added to both designs to play their roles as to efficiency increase. By doing so, the revised load modulation based DPA has the maximum PAE of 39.6%, maximum output power ( P out ) of 31.61dBm, at 8 GHz. Simulation results of this DPA in higher harmonics indicate the designed DPA has the minimum second and third harmonics power of -51.7 dBm and -80 dBm, respectively. For the sake of linearity evaluation, it is depicted that 1dB-power gain compression has not occurred in the input power (P in ) range in which the proposed DPA works.

scholarly journals Linearization of broadband microwave amplifier

2014 ◽  
Vol 11 (1) ◽  
pp. 111-120 ◽  
Author(s):  
Aleksandra Djoric ◽  
Natasa Males-Ilic ◽  
Aleksandar Atanaskovic ◽  
Bratislav Milovanovic
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Transmission Lines ◽  
Maximum Output Power ◽  
Input Power ◽  
Maximum Output ◽  
Frequency Range ◽  
Microwave Amplifier ◽  
Lumped Element ◽  
Input And Output

The linearization of broadband power amplifier for application in the frequency range 0.9-1.3 GHz is considered in this paper. The amplifier is designed for LDMOSFET characterized by the maximum output power 4W designing the broadband lumped element matching circuits and matching circuits in topologies that combines LC elements and transmission lines. The linearization of the amplifier is carried out by the second harmonics of the fundamental signals injected at the input and output of the amplifier transistor. The effects of linearization are considered for the case of two sinusoidal signals separated in frequency by different intervals up to 80 MHz ranging input power levels to saturation.

scholarly journals A Comprehensive Harmonic Analysis of Current-Mode Power Amplifiers

Energies ◽  
2021 ◽  
Vol 14 (21) ◽  
pp. 7042
Author(s):  
Chiara Ramella ◽  
Paolo Colantonio ◽  
Marco Pirola
Keyword(s):  
Theoretical Analysis ◽  
Power Amplifier ◽  
Power Amplifiers ◽  
Maximum Output Power ◽  
Average Power ◽  
Current Mode ◽  
Input Power ◽  
Maximum Output ◽  
Square Wave ◽  
Source Current

This work presents a comprehensive theoretical analysis of current-mode power amplifiers as a function of input power for different biasing classes under the common simplifying assumption of constant transconductance and hard current cut-off/saturation. Typically, the theoretical analysis of power amplifier performance and behavior are carried out only at maximum output power. However, to achieve high data-rates, modern telecommunication systems adopt signals characterized by a very high peak-to-average power ratio, thus it is useful to analyze the power amplifier behavior as a function of power back-off. Moreover, in many cases, to enhance the efficiency and/or to apply harmonic shaping techniques, a clipped drain-source current, which approaches a square wave, is required. The classical analysis can be extended to low power levels only under the assumption of power-independent conduction angle, which is true only for class-A and class-B amplifiers, and does not take into account possible waveform clipping at maximum current. This work presents a complete theoretical Fourier analysis of FET-based power amplifiers as a function of quiescent drain-source current at any input power level and accounting for the clipped current case, up to the square-wave limit, reorganizing and completing the material that can be found in classical textbooks in the field.

scholarly journals ANALYSES OF THE THERMAL EFFICIENCY AND THE OUTPUT POWER IN A JOULE-BRAYTON CYCLE

2009 ◽  
Vol 12 (4) ◽  
pp. 39-46
Author(s):  
Kien Chi Le
Keyword(s):  
Output Power ◽  
Thermal Efficiency ◽  
High Efficiency ◽  
Pressure Ratio ◽  
Maximum Output Power ◽  
Maximum Temperature ◽  
Maximum Efficiency ◽  
Maximum Output ◽  
Brayton Cycle ◽  
Compressor Inlet

The analyses on Joule-Brayton cycle, which could be used for a high efficiency power generation system, using the temperature and the pressure of compressor have been carried out. As a result, when the ratio of maximum temperature to the minimum temperature in the cycle increased, the thermal efficiency increased. By analyzing the efficiency and the output power, it is understood that the ratio of compressor outlet pressure to the compressor inlet pressure, as well as the pressure ratio across the compressor for maximum thermal efficiency and maximum output power are different. The maximum thermal efficiency could be an important technical parameter; however, the maximum output power is significant in the cost and the size of system. For that reason, depending on the required system for maximum efficiency or for maximum power, the ratio of temperature and pressure are designed

DOUBLE SUPPLY, LINEAR, AND HIGH EFFICIENCY PUSH AMPLIFIER DESIGN FOR ENVELOPE TRACKING POWER AMPLIFIERS IN WiMAX APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450113 ◽  
Author(s):  
MOHAMMAD MOGHADDAM TABRIZI ◽  
NASSER MASOUMI
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
High Performance ◽  
High Efficiency ◽  
Maximum Output Power ◽  
Total Efficiency ◽  
Maximum Output ◽  
Error Vector Magnitude ◽  
Power Added Efficiency ◽  
Amplifier Design

In this work, a novel and efficient approach is proposed to optimize linearity and efficiency of a power amplifier used in mobile communication applications. A linear and high performance push amplifier is designed and analyzed to extract design equations for an optimum performance. The proposed push amplifier has two sections; an analog section and a switching section. The analog section provides the required linearity and the switching section guarantees the satisfaction of the total efficiency level. Double power supply scheme is used in push amplifiers to enhance its performance. Two separate power supplies are employed for linear and switching sections of push amplifiers which have different voltage levels. The implemented circuit is simulated using HSPICERF with TSMC models for active and passive elements. The proposed power amplifier (PA) provides a maximum output power of 25 dBm and power added efficiency (PAE) as high as 51% at 2.5 GHz operation frequency. At 1-dB compression point, this PA exhibits output power of 25 dBm with 48% PAE and 4.5% error vector magnitude (EVM) which is appropriate for 64QAM OFDM signals.

A fully matched dual stage CMOS power amplifier with integrated passive linearizer attaining 23 db gain, 40% PAE and 28 DBM OIP3

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Premmilaah Gunasegaran ◽  
Jagadheswaran Rajendran ◽  
Selvakumar Mariappan ◽  
Yusman Mohd Yusof ◽  
Zulfiqar Ali Abdul Aziz ◽  
...  
Keyword(s):  
Power Consumption ◽  
Output Power ◽  
Power Amplifier ◽  
Maximum Output Power ◽  
Maximum Output ◽  
Power Gain ◽  
Matching Network ◽  
Content Type ◽  
Power Added Efficiency ◽  
Main Amplifier

Purpose The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA). Design/methodology/approach The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability. Findings With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation. Practical implications The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design. Originality/value The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

scholarly journals A Power Amplifier with Large High-Efficiency Range for 5G Communication

Sensors ◽  
2020 ◽  
Vol 20 (19) ◽  
pp. 5581
Author(s):  
Zhiwei Zhang ◽  
Zhiqun Cheng ◽  
Guohua Liu
Keyword(s):  
Output Power ◽  
Design Process ◽  
Power Amplifier ◽  
High Efficiency ◽  
New Method ◽  
Saturated Output Power ◽  
Doherty Power Amplifier ◽  
5G Communication

This paper presents a new method to design a Doherty power amplifier (DPA) with a large, high-efficiency range for 5G communication. This is through analyzing the drain-to-source capacitance (CDS) of DPAs, and adopting appropriate impedance of the peak device. A closed design process is proposed, to design the extended efficiency range DPA based on derived theories. For validation, a DPA with large efficiency range was designed and fabricated by using two equal devices. The measured results showed that the saturated output power was between 43.4 dBm and 43.7 dBm in the target band. Around 70% saturated drain efficiency is obtained with a gain of greater than 11 dB. Moreover, the obtained drain efficiency is larger than 50% at the 10 dB power back-off, when operating at 3.5 GHz. These superior performances illustrate that the implemented DPA can be applied well in 5G communication.

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