scholarly journals A Comprehensive Harmonic Analysis of Current-Mode Power Amplifiers

Energies ◽  
2021 ◽  
Vol 14 (21) ◽  
pp. 7042
Author(s):  
Chiara Ramella ◽  
Paolo Colantonio ◽  
Marco Pirola
Keyword(s):  
Theoretical Analysis ◽  
Power Amplifier ◽  
Power Amplifiers ◽  
Maximum Output Power ◽  
Average Power ◽  
Current Mode ◽  
Input Power ◽  
Maximum Output ◽  
Square Wave ◽  
Source Current

This work presents a comprehensive theoretical analysis of current-mode power amplifiers as a function of input power for different biasing classes under the common simplifying assumption of constant transconductance and hard current cut-off/saturation. Typically, the theoretical analysis of power amplifier performance and behavior are carried out only at maximum output power. However, to achieve high data-rates, modern telecommunication systems adopt signals characterized by a very high peak-to-average power ratio, thus it is useful to analyze the power amplifier behavior as a function of power back-off. Moreover, in many cases, to enhance the efficiency and/or to apply harmonic shaping techniques, a clipped drain-source current, which approaches a square wave, is required. The classical analysis can be extended to low power levels only under the assumption of power-independent conduction angle, which is true only for class-A and class-B amplifiers, and does not take into account possible waveform clipping at maximum current. This work presents a complete theoretical Fourier analysis of FET-based power amplifiers as a function of quiescent drain-source current at any input power level and accounting for the clipped current case, up to the square-wave limit, reorganizing and completing the material that can be found in classical textbooks in the field.

scholarly journals Design and simulate a doherty power amplifier using GaAs technology for telecommunication applications

2019 ◽  
Vol 15 (2) ◽  
pp. 845
Author(s):  
Ehsan Barmala
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Power Amplifiers ◽  
High Efficiency ◽  
Maximum Output Power ◽  
Input Power ◽  
Power Divider ◽  
Maximum Efficiency ◽  
Maximum Output ◽  
Doherty Power Amplifier

<span>In this paper, a Doherty power amplifier was designed and simulated at 2.4 GHz central frequency which has high efficiency. A Doherty power amplifier is a way to increase the efficiency in the power amplifiers. OMMIC ED02AH technology and PHEMT transistors, which is made of gallium arsenide, have been used in this simulation. The Doherty power amplifier unique feature is its simple structure which is consisting of two parallel power amplifiers and transmission lines. In order to integrate the circuit, the Doherty power transmission amplifier lines were implemented using an inductor and capacitive components. Also, the Wilkinson power divider is used on the chip input. To improve the efficiency, the auxiliary amplifier dimensions is selected enlarge and the further input power is allocated it by the power divider. A parallel R-C circuit has been used at the input of transistors to improve their stability. Simulation results show that the Doherty power amplifier has 17.2 dB output power gain, 23 dBm maximum output power, and its output power P<sub>1dB</sub> =22.6dBm at compression point -1 dB, also, its maximum efficiency is 55.5%.</span>

scholarly journals Extended Bandwidth and Increased Efficiency Quasi-Doherty Power Amplifier Design With A Revised Approach For Load Modulation

2021 ◽  
Author(s):  
Seyedehmarzieh Rouhani ◽  
Kasra Rouhi ◽  
Adib Abrishamifar ◽  
Majid Tayarani
Keyword(s):  
Power Amplifier ◽  
High Power ◽  
Maximum Output Power ◽  
Input Power ◽  
Maximum Efficiency ◽  
Maximum Output ◽  
Power Added Efficiency ◽  
Active Feedback ◽  
Doherty Power Amplifier ◽  
Load Modulation

This paper presents an approach to power added efficiency (PAE) increase for Quasi-Doherty power amplifier (Q-DPA) design. For this aim, active feedback is utilized instead of a passive quarter wavelength transmission line (TL) usage, which is conventionally used in the DPA schematic. PAE increase can be done by applying an accurate load modulation to the main amplifier (PAmain), especially for technologies in which output impedance of the main power amplifier (Zout,main) considerably varies in both low and high power regions. Because such precise modulation is still based on a modified TL, this approach suffers from the inherent narrowband behavior of that TL. As a consequence, expecting a wideband DPA may not be satisfied in all cases. To deal with this issue, active feedback is used to play a role in reaching PAmain, which is not saturated before, to its maximum efficiency at the highest level of received input power (Pin) in the high power region. Following Zout,main trajectories in power and frequency sweeps simultaneously just by a passive TL are not needed anymore. Still, for the sake of preventing total PAE degradation due to the consummated power by the feedback path’s power amplifier (PAfeedback) should be limited, analytical confinement is provided in this work. A comparison is made between GaAs pHEMT 0.25um MMIC technology-based conventional DPA and the proposed revised approach based-DPA to verify the mentioned approach. The proposed PA shows maximum output power of 33.4 dBm, maximum PAE of 41.6, fractional bandwidth of 11%. The Q-DPA works with a maximum power gain of 24.16.

scholarly journals Increased Efficiency of a Current Compensating Load Modulation Based MMIC Doherty Power Amplifier Design In 0.25m GaAs pHEMT Technology

2020 ◽  
Author(s):  
Seyedehmarzieh Rouhani ◽  
Kasra Rouhi ◽  
Adib Abrishamifar ◽  
Majid Tayarani
Keyword(s):  
Power Amplifier ◽  
Second Harmonic ◽  
Maximum Output Power ◽  
Input Power ◽  
Maximum Output ◽  
Modulation Equation ◽  
Gain Compression ◽  
Power Added Efficiency ◽  
Doherty Power Amplifier ◽  
Load Modulation

In this work, a premise is applied to the conventional load modulation equation of Doherty power amplifier (DPA) in 0.25 m GaAs pHEMT technology to compensate output impedance of main amplifier ( Z out,main ) variation, even in low power region. Using this modified modulation leads to the DPAs power added efficiency (PAE) increase in comparison by the case in which the load modulation revision is ignored, which is also designed in this paper. Second harmonic rejection networks are also added to both designs to play their roles as to efficiency increase. By doing so, the revised load modulation based DPA has the maximum PAE of 39.6%, maximum output power ( P out ) of 31.61dBm, at 8 GHz. Simulation results of this DPA in higher harmonics indicate the designed DPA has the minimum second and third harmonics power of -51.7 dBm and -80 dBm, respectively. For the sake of linearity evaluation, it is depicted that 1dB-power gain compression has not occurred in the input power (P in ) range in which the proposed DPA works.

scholarly journals Linearization of broadband microwave amplifier

2014 ◽  
Vol 11 (1) ◽  
pp. 111-120 ◽  
Author(s):  
Aleksandra Djoric ◽  
Natasa Males-Ilic ◽  
Aleksandar Atanaskovic ◽  
Bratislav Milovanovic
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Transmission Lines ◽  
Maximum Output Power ◽  
Input Power ◽  
Maximum Output ◽  
Frequency Range ◽  
Microwave Amplifier ◽  
Lumped Element ◽  
Input And Output

The linearization of broadband power amplifier for application in the frequency range 0.9-1.3 GHz is considered in this paper. The amplifier is designed for LDMOSFET characterized by the maximum output power 4W designing the broadband lumped element matching circuits and matching circuits in topologies that combines LC elements and transmission lines. The linearization of the amplifier is carried out by the second harmonics of the fundamental signals injected at the input and output of the amplifier transistor. The effects of linearization are considered for the case of two sinusoidal signals separated in frequency by different intervals up to 80 MHz ranging input power levels to saturation.

scholarly journals Machine-Learning Assisted Optimisation of Free-Parameters of a Dual-Input Power Amplifier for Wideband Applications

Sensors ◽  
2021 ◽  
Vol 21 (8) ◽  
pp. 2831
Author(s):  
Teng Wang ◽  
Wantao Li ◽  
Roberto Quaglia ◽  
Pere L. Gilabert
Keyword(s):  
Power Amplifier ◽  
Power Efficiency ◽  
Average Power ◽  
Long Term Evolution ◽  
Input Power ◽  
Global Optimisation ◽  
Power Ratio ◽  
Term Evolution ◽  
Free Parameters

This paper presents an auto-tuning approach for dual-input power amplifiers using a combination of global optimisation search algorithms and adaptive linearisation in the optimisation of a multiple-input power amplifier. The objective is to exploit the extra degrees of freedom provided by dual-input topologies to enhance the power efficiency figures along wide signal bandwidths and high peak-to-average power ratio values, while being compliant with the linearity requirements. By using heuristic search global optimisation algorithms, such as the simulated annealing or the adaptive Lipschitz Optimisation, it is possible to find the best parameter configuration for PA biasing, signal calibration, and digital predistortion linearisation to help mitigating the inherent trade-off between linearity and power efficiency. Experimental results using a load-modulated balanced amplifier as device-under-test showed that after properly tuning the selected free-parameters it was possible to maximise the power efficiency when considering long-term evolution signals with different bandwidths. For example, a carrier aggregated a long-term evolution signal with up to 200 MHz instantaneous bandwidth and a peak-to-average power ratio greater than 10 dB, and was amplified with a mean output power around 33 dBm and 22.2% of mean power efficiency while meeting the in-band (error vector magnitude lower than 1%) and out-of-band (adjacent channel leakage ratio lower than −45 dBc) linearity requirements.

A fully matched dual stage CMOS power amplifier with integrated passive linearizer attaining 23 db gain, 40% PAE and 28 DBM OIP3

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Premmilaah Gunasegaran ◽  
Jagadheswaran Rajendran ◽  
Selvakumar Mariappan ◽  
Yusman Mohd Yusof ◽  
Zulfiqar Ali Abdul Aziz ◽  
...  
Keyword(s):  
Power Consumption ◽  
Output Power ◽  
Power Amplifier ◽  
Maximum Output Power ◽  
Maximum Output ◽  
Power Gain ◽  
Matching Network ◽  
Content Type ◽  
Power Added Efficiency ◽  
Main Amplifier

Purpose The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA). Design/methodology/approach The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability. Findings With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation. Practical implications The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design. Originality/value The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

scholarly journals D-Band Frequency Tripler Module Using Anti-Parallel Diode Pair and Waveguide Transitions

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1201
Author(s):  
Jihoon Doo ◽  
Jongyoun Kim ◽  
Jinho Jeong
Keyword(s):  
Input Signal ◽  
Low Cost ◽  
Impedance Matching ◽  
Maximum Output Power ◽  
Input Power ◽  
Maximum Output ◽  
Band Frequency ◽  
Circuit Components ◽  
Plane Probe ◽  
Harmonic Components

In this paper, D-band (110–170 GHz) frequency tripler module is presented using anti-parallel GaAs Schottky diode pair and waveguide-to-microstrip transitions. The anti-parallel diode pair is used as a nonlinear device generating harmonic components for Q-band input signal (33–50 GHz). The diode is zero-biased to eliminate the bias circuits and thus minimize the number of circuit components for low-cost hybrid fabrication. The anti-parallel connection of two identical diodes effectively suppresses DC and even harmonics in the output. Furthermore, the first and second harmonics of Q-band input signal are cut off by D-band rectangular waveguide. Input and output impedance matching networks are designed based on the optimum impedances determined by harmonic source- and load-pull simulations using the developed nonlinear diode model. Waveguide-to-microstrip transitions at Q- and D-bands are also designed using E-plane probe to package the frequency tripler in the waveguide module. The compensation circuit is added to reduce the impedance mismatches by bond-wires connecting two separate substrates. The fabricated frequency tripler module produces a maximum output power of 5.4 dBm at 123 GHz under input power of 20.5 dBm. A 3 dB bandwidth is as wide as 22.5% from 118.5 to 148.5 GHz at the input power of 15.0 dBm. This result corresponds to the excellent bandwidth performance with a conversion gain comparable to the previously reported frequency tripler operating at D-band.

Design of a 0.7~2.6GHz Wideband Power Amplifier in 0.18-μm CMOS Process

2014 ◽  
Vol 618 ◽  
pp. 543-547
Author(s):  
Zhou Yu ◽  
Xiang Ning Fan ◽  
Zai Jun Hua ◽  
Chen Xu
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Negative Feedback ◽  
Maximum Output Power ◽  
Cmos Process ◽  
Maximum Output ◽  
Power Gain ◽  
Class A ◽  
Simulation Results ◽  
Multi Mode

A power amplifier (PA) for multi-mode multi-standard transceiver which is implemented in a TSMC 0.18μm process is presented. The proposed PA uses matching compensation, lossy matching network and negative feedback technique to improve bandwidth. To achieve the linearity performance, the two-stage PA operates in Class-A regime. Simulation results show that the power amplifier achieves maximum output power of more than 24dBm in 0.7~2.6GHz. The output P1dBof the PA is larger than 22dBm. The simulated power gain is more than 27dB. The S11 is less than-10dB and the S22 is under-5dB.

Concurrent dual-band SiGe HBT power amplifier for Wireless applications

2009 ◽  
Vol 1 (2) ◽  
pp. 117-126 ◽  
Author(s):  
Vittorio Camarchia ◽  
Rocco Giofrè ◽  
Iacopo Magrini ◽  
Luca Piazzon ◽  
Alessandro Cidronali ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Orthogonal Frequency Division Multiplexing ◽  
Maximum Output Power ◽  
System Level ◽  
Dual Band ◽  
Maximum Output ◽  
System Architectures ◽  
Power Added Efficiency ◽  
Mode Operation

This paper presents an investigation of a concurrent low-cost dual-band power amplifier (PA) fabricated in SiGe technology, able to simultaneously operate at two frequencies of 2.45 and 3.5-GHz, including an evaluation of its system level performance potentiality. Taking into account the technology novelty and the lack of device characterization and modeling, a hybrid (MIC) approach has been adopted both for a fast prototyping of the PA and for the evaluation of the device potentiality based on an extensive linear and nonlinear characterization. The comparison of PA performance in single-band or concurrent mode operation will be presented. In particular, the measured PA prototype shows an output power of 17.2 and 17-dBm at a 1-dB compression point, at 2.45 and 3.5-GHz, respectively, for CW single-mode operation, with a power added efficiency around 20%. System-level analysis predicts that, when the PA is operated under the 20-MHz Orthogonal Frequency-Division Multiplexing (OFDM) concurrent signals, the maximum output power levels to maintain the Error Vector Magnitude (EVM) within 5% are 11 and 3.5-dBm at 2.45 and 3.5-GHz, respectively. Moreover, new concepts and possible new system architectures for the development of the next generation of the multi-band transceiver front-end will be provided with an extensive system-level evaluation of the amplifier.

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