Dynamic Partial Reconfiguration with FIR Filter Application

2015 ◽  
Vol 4 (3) ◽  
pp. 201
Author(s):  
Noopur Astik
Keyword(s):  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Partial Reconfiguration ◽  
Dynamic Partial Reconfiguration ◽  
Pass Filter ◽  
Direct Form ◽  
Field Programmable ◽  
Low Pass ◽  
High Pass

Dynamic partial reconfiguration has evolved as a very prominent state of art for efficient area utilization of <em>Field Programmable Gate Array</em> (FPGA) as well as significant reduction in its overall power consumption when properly used to lessen the idle logic on FPGA. It provides desired results even as the computational complexity increases in the field of Digital Signal Processing. This paper explains Dynamic Partial Reconfiguration (DPR) with an example of Finite Impulse response (FIR) filter of order 10. Initially RTL coding for Direct Form FIR structure is written in Verilog in fixed point format for low pass and high pass filter modules using ISE Design suite. Functioning of the both the modules is verified individually through hardware co-simulation on ZYBO (Zynq Board) from Digilent using Black Box from System Generator. Finally dynamic partial reconfigurable FIR filter with low pass and high pass as reconfigurable modules is implemented on ZYBO using PlanAhead tool. Final comparison of resource utilization with and without DPR is presented

Implementation of the Finite Impulse Response (FIR) Filter on the DSK TMS320C6713 Transceiver Using Windowing Techniques

2018 ◽  
Vol 6 (1) ◽  
pp. 1-8
Author(s):  
Adella Acqha Vico Addina
Keyword(s):  
Filter Design ◽  
Finite Impulse Response ◽  
Bandpass Filters ◽  
Fir Filter ◽  
Test Results ◽  
Rectangular Window ◽  
Filter Performance ◽  
Highpass Filter ◽  
Low Pass ◽  
High Pass

In this study, implementing the FIR filter with the Blackman window and Rectangular window methods with the types of low pass, highpass, and bandpass filters using 2 DSK TMS320C6713 boards as sender (Tx) and receiver (Rx) using the code composer studio (CCS) V software program. .3.1, which will then be displayed on Matlab to observe the output results. From the test results, data will be obtained which are then analyzed to determine the filter performance of the design results and the real implementation results using the DSK TMS320C6713. The results showed that the design of the low pass, high pass and bandpass filters was in accordance with the desired specifications, although in the highpass filter design, the filter results were still incomplete.

scholarly journals Minimizing Design Costs of an FIR Filter Using a Novel Coefficient Optimization Algorithm

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Ming-Chih Chen ◽  
Tsung-Ting Chen
Keyword(s):  
Optimization Algorithm ◽  
Collision Detection ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Pass Band ◽  
Low Pass ◽  
Coefficient Optimization ◽  
Canonic Signed Digit ◽  
Common Subexpressions ◽  
High Pass

This work presents a novel coefficient optimization algorithm to reduce the area and improve the performance of finite impulse response (FIR) filter designs. Two basic architectures are commonly used in filters—direct and transposed. The coefficients of a filter can be encoded in the fewest possible nonzero bits using canonic signed digit (CSD) expressions. The proposed optimization algorithm can share common subexpressions (CS) and reduce the number of replicate operations that involve the CSD coefficients of filters with a transposed architecture. The effectiveness of the algorithm is confirmed by using filters with the collision detection multiple access (CDMA) standard, the 121-tap high-pass band, and 105- and 325-tap low-pass bands as benchmarks. For example, the proposed algorithm used in the optimization of 105-tap filter has a 30.44% smaller combinational logic area and a 16.69% better throughput/area than those of the best design that has been developed to date. Experimental results reveal that the proposed algorithm outperforms earlier designs.

scholarly journals DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS

2017 ◽  
Vol 10 (13) ◽  
pp. 66
Author(s):  
A Aparna ◽  
T Vigneswaran
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Research Work ◽  
Digital Signal ◽  
Fir Filter ◽  
Pass Filter ◽  
Finite Impulse Response Filters

This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications. 

scholarly journals Minimization of SIDELOBE Attenuation and Power of a Fir Low Pass Filter using FRFT and CSD Algorithm

2020 ◽  
Vol 9 (5) ◽  
pp. 1380-1383
Keyword(s):  
Fourier Transform ◽  
Communication Systems ◽  
Finite Impulse Response ◽  
Side Lobe ◽  
Fir Filter ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Canonical Signed Digit ◽  
Low Pass ◽  
Two Parameters

For digital signal processing, communication systems and VLSI design architectures, an efficient FIR filter is required to eliminate the noise signals. To design an efficient FIR filter, the minimization of two parameters is required such as side lobe attenuation and power. These two parameters can be achieved by designing a FIR filter with the help of Fractional Fourier Transform (FrFT) and Canonical Signed digit (CSD) algorithm. In this work, Finite Impulse Response (FIR) low pass filter is designed by using both FrFT and ordinary Fourier Transform (FT) methods and their frequency responses are compared in terms of side lobe attenuation (SLA). After comparison of both methods, the better results are obtained for an FrFT based design of FIR low pass filter. Apart from this, the FrFT based design of FIR low pass filter is realized in direct form architecture and implemented in VLSI. Further, the Canonical Signed digit (CSD) algorithm is applied for the multiplication process in the architecture implementation to minimize the power consumption. Moreover, frequency response of FIR low pass filter is obtained by using MATLAB software and simulation and synthesis results are obtained by using Xilinx 13.1 ISE.

Design and implementation of pervasive DA based FIR filter and feeder register based multiplier for software definedradio networks

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Mohan Kumar ◽  
Ranga Raju
Keyword(s):  
Energy Efficiency ◽  
Impulse Response ◽  
Power Dissipation ◽  
Software Defined Radio ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Infinite Impulse Response ◽  
Content Type ◽  
Field Programmable

Purpose Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization. Design/methodology/approach The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324. Findings The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively. Originality/value The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

scholarly journals Systolic Fir Filter using Bypass Multiplier

2019 ◽  
Vol 9 (2) ◽  
pp. 3472-3474
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
Large Scale ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Filter Method ◽  
Design Complexity ◽  
Field Programmable ◽  
Scale Integration

In DSP the most common function is Finite Impulse Response (FIR) filter which is realized in field Programmable gate Arrays (FPGAs). For efficient Very Large Scale Integration (VLSI) computation systolic FIR filter architecture has attractive models. High speed is the major concern for fast computation in real time Digital Signal Processing (DSP) applications. In conventional systolic FIR filter method uses general array multiplier structure which takes more time to compute the process with high design complexity with less power. To overcome this problem the systolic FIR filter utilizing Bypass Feed Direct Multiplier(BFDM) is proposed. The proposed method 16 tap systolic FIR parallel processing offers less delay with less design complexity which is used in image and signal processing applications. The proposed method is simulated using Xilinx ISE 12.4 ISE tool and the functions are evaluated by MODELSIM 6.3C.

scholarly journals VLSI Design and Implementation for Adaptive Filter using LMS Algorithm

2012 ◽  
pp. 297-301
Author(s):  
Asit Kumar Subudhi ◽  
Biswajit Mishra ◽  
Mihir N. Mohanty
Keyword(s):  
High Performance ◽  
Adaptive Filters ◽  
Finite Impulse Response ◽  
Vlsi Design ◽  
Digital Signal ◽  
Fir Filter ◽  
Lms Algorithm ◽  
Least Mean Square ◽  
Field Programmable ◽  
Adaptive Noise

Adaptive filters, as part of digital signal systems, have been widely used, as well as in applications such as adaptive noise cancellation, adaptive beam forming, channel equalization, and system identification. However, its implementation takes a great deal and becomes a very important field in digital system world. When FPGA (Field Programmable Logic Array) grows in area and provides a lot of facilities to the designers, it becomes an important competitor in the signal processing market. In general FIR structure has been used more successfully than IIR structure in adaptive filters. However, when the adaptive FIR filter was made this required appropriate algorithm to update the filter’s coefficients. The algorithm used to update the filter coefficient is the Least Mean Square (LMS) algorithm which is known for its simplification, low computational complexity, and better performance in different running environments. When compared to other algorithms used for implementing adaptive filters the LMS algorithm is seen to perform very well in terms of the number of iterations required for convergence. This phenomenon can be achieved by a sufficient choice of bit length to represent the filter’s coefficients. This paper presents a lowcost and high performance programmable digital finite impulse response (FIR) filter. It follows the adaptive algorithm used for the development of the system. The architecture employs the computation sharing algorithm to reduce the computation complexity.

A semi-lumped microstrip UWB bandpass filter

2009 ◽  
Vol 1 (1) ◽  
pp. 57-64 ◽  
Author(s):  
Darine Kaddour ◽  
Jean-Daniel Arnould ◽  
Philippe Ferrari
Keyword(s):  
Group Delay ◽  
Bandpass Filter ◽  
Filter Design ◽  
Sensitivity Study ◽  
Critical Parameters ◽  
Center Frequency ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass ◽  
High Pass

In this paper, a miniaturized bandpass filter for ultra-wide-band applications is proposed. It is based on the embedding of high-pass structures in a low-pass filter. A semi-lumped technology combining surface-mounted capacitors and transmission lines has been used. The filter design rules have been carried out. Furthermore, two filters having a 3-dB fractional bandwidth of 142 and 150%, centered at 0.77 and 1 GHz, respectively, have been realized for a proof of concept. Measured characteristics, in good agreement with simulations, show attractive properties of return loss (|S11| <−18 dB), insertion loss (<0.3 dB), and a maximum group delay and group delay variation of 2 and 1.3 ns, respectively. A distributed filter based on the same low-pass/high-pass approach has been also realized and measured for comparison. The size reduction reaches 85% for the semi-lumped filter, and its selectivity is improved with a shape factor of 1.3:1 instead of 1.5:1. The semi-lumped filter's drawback is related to a smaller rejection bandwidth compared to the distributed one. To improve the high-frequency stopband, an original technique for spurious responses suppression based on capacitively loaded stubs has been proposed. Even if the performances do not reach that obtained for the distributed approach, with this technique spurious responses are pushed until eight times the center frequency. A sensitivity study vs. critical parameters has also been carried out, showing the robustness of the design.

scholarly journals Design and Implementation of Digital Filters for ECG Data Based on Field Programmable Gate Array and MATLAB

2020 ◽  
pp. 17-19
Author(s):  
Emre Cancioglu ◽  
Gokberk Cakiroglu ◽  
Alkim Gokcen ◽  
Yilmaz Sefa Altanay
Keyword(s):  
Digital Filters ◽  
Pass Band ◽  
System Generator ◽  
Design And Implementation ◽  
Field Programmable ◽  
Low Pass ◽  
Band Pass ◽  
Database Platform ◽  
High Pass ◽  
Ecg Data

This study provides design and implementation of four digital filters (low pass, high pass, band pass and band stop) for ECG (electrocardiogram) data on FPGA with MATLAB by a serial communication. The study is conducted with using ECG data which is obtained from PhysioBank Database platform. SysGen (System Generator for DSP) which is a toolbox for MATLAB is used for designing and implementing the digital filters. The aim of the study is to perform four different digital filters with various blocks on the SysGen Toolbox. The study then examines the results of four different digital filters.

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