scholarly journals Minimizing Design Costs of an FIR Filter Using a Novel Coefficient Optimization Algorithm

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Ming-Chih Chen ◽  
Tsung-Ting Chen

This work presents a novel coefficient optimization algorithm to reduce the area and improve the performance of finite impulse response (FIR) filter designs. Two basic architectures are commonly used in filters—direct and transposed. The coefficients of a filter can be encoded in the fewest possible nonzero bits using canonic signed digit (CSD) expressions. The proposed optimization algorithm can share common subexpressions (CS) and reduce the number of replicate operations that involve the CSD coefficients of filters with a transposed architecture. The effectiveness of the algorithm is confirmed by using filters with the collision detection multiple access (CDMA) standard, the 121-tap high-pass band, and 105- and 325-tap low-pass bands as benchmarks. For example, the proposed algorithm used in the optimization of 105-tap filter has a 30.44% smaller combinational logic area and a 16.69% better throughput/area than those of the best design that has been developed to date. Experimental results reveal that the proposed algorithm outperforms earlier designs.

2018 ◽  
Vol 6 (1) ◽  
pp. 1-8
Author(s):  
Adella Acqha Vico Addina

In this study, implementing the FIR filter with the Blackman window and Rectangular window methods with the types of low pass, highpass, and bandpass filters using 2 DSK TMS320C6713 boards as sender (Tx) and receiver (Rx) using the code composer studio (CCS) V software program. .3.1, which will then be displayed on Matlab to observe the output results. From the test results, data will be obtained which are then analyzed to determine the filter performance of the design results and the real implementation results using the DSK TMS320C6713. The results showed that the design of the low pass, high pass and bandpass filters was in accordance with the desired specifications, although in the highpass filter design, the filter results were still incomplete.


Author(s):  
Noopur Astik

Dynamic partial reconfiguration has evolved as a very prominent state of art for efficient area utilization of <em>Field Programmable Gate Array</em> (FPGA) as well as significant reduction in its overall power consumption when properly used to lessen the idle logic on FPGA. It provides desired results even as the computational complexity increases in the field of Digital Signal Processing. This paper explains Dynamic Partial Reconfiguration (DPR) with an example of Finite Impulse response (FIR) filter of order 10. Initially RTL coding for Direct Form FIR structure is written in Verilog in fixed point format for low pass and high pass filter modules using ISE Design suite. Functioning of the both the modules is verified individually through hardware co-simulation on ZYBO (Zynq Board) from Digilent using Black Box from System Generator. Finally dynamic partial reconfigurable FIR filter with low pass and high pass as reconfigurable modules is implemented on ZYBO using PlanAhead tool. Final comparison of resource utilization with and without DPR is presented


2007 ◽  
Vol 16 (04) ◽  
pp. 507-516 ◽  
Author(s):  
SHAHRAM MINAEI ◽  
ERKAN YUCE

In this paper, a universal current-mode second-order active-C filter for simultaneously realizing low-pass, band-pass and high-pass responses is proposed. The presented filter employs only three plus-type second-generation current-controlled conveyors (CCCII+s). This filter needs no critical active and passive component matching conditions and no additional active and passive elements for realizing high output impedance low-pass, band-pass and high-pass characteristics. The angular resonance frequency (ω0) and quality factor (Q) of the proposed resistorless filter can be tuned electronically. To verify the theoretical analysis and to exhibit the performance of the proposed filter, it is simulated with SPICE program.


2005 ◽  
Vol 14 (01) ◽  
pp. 159-164 ◽  
Author(s):  
SUDHANSHU MAHESHWARI ◽  
IQBAL A. KHAN

A novel voltage-mode universal filter employing only two current differencing buffered amplifiers (CDBAs) is proposed. The filter uses four inputs and single output to realize six responses, viz. low-pass, high-pass, inverting band-pass, noninverting band-pass, band-elimination, and all-pass through input selection with independent pole-Q control. Computer simulation results using SPICE are also given to verify the theory.


Author(s):  
Emre Cancioglu ◽  
Gokberk Cakiroglu ◽  
Alkim Gokcen ◽  
Yilmaz Sefa Altanay

This study provides design and implementation of four digital filters (low pass, high pass, band pass and band stop) for ECG (electrocardiogram) data on FPGA with MATLAB by a serial communication. The study is conducted with using ECG data which is obtained from PhysioBank Database platform. SysGen (System Generator for DSP) which is a toolbox for MATLAB is used for designing and implementing the digital filters. The aim of the study is to perform four different digital filters with various blocks on the SysGen Toolbox. The study then examines the results of four different digital filters.


Author(s):  
Umar Mohammad ◽  
Fang Tang ◽  
Shu Zhou ◽  
Mohd Yusuf Yasin

A new study imitating the design and implementation of single-input–single-output (SISO) filters as bilateral filters has been presented in this paper. Second generation current controlled current conveyor (CCCII), being a popular low power active element was considered for the realization of the proposed design. Complete design, analysis and implementation of the voltage mode SISO filter was done using only two CCCII’s and two passive parasitic components. The striking feature of this work is that the proposed design can be made to work at either the input node or the output node, as well as in the cases; the change of direction changes the filter into an inverse filter and buffer filter. Basic filter applications like low-pass, high-pass, band-pass and band-stop were aimed to check the uniformity of the proposed design at different frequencies. Results perceived from the simulation study were fare enough on both the side nodes of the proposed design. Categorically, the circuit can be aimed to work in lieu of a filter transceiver. The consistency of the circuit was analyzed by the nodal analysis. Whereas the working performance was enormously analyzed and evaluated during the simulation analysis. The proposed design was simulated in HSPICE tool to exhibit and exploit the delivery, using the 45[Formula: see text]nm predictive technology model (PTM) parameters, with [Formula: see text][Formula: see text]V rail to rail voltages. Maximum power consumption of the circuit is around 138.5[Formula: see text][Formula: see text]W. Finally, the design was also implemented in Cadence Virtuoso using 40[Formula: see text]nm SMIC parameters.


2016 ◽  
Vol 25 (12) ◽  
pp. 1650154 ◽  
Author(s):  
Ahmet Abaci ◽  
Erkan Yuce

In this paper, two new second-order voltage-mode universal filters are proposed. Both of the proposed filters use only two differential voltage current conveyors (DVCCs), four resistors and two grounded capacitors which are advantageous from integrated circuit technology point of view. They can simultaneously provide second-order low-pass, high-pass, band-pass, notch and all-pass responses. They offer orthogonal control of angular resonance frequency and quality factor. However, they have a single matching condition for only all-pass responses. A number of simulations based on SPICE program are accomplished in order to demonstrate the performance of both filters.


2011 ◽  
Vol 20 (03) ◽  
pp. 549-555 ◽  
Author(s):  
A. K. SINGH ◽  
R. SENANI ◽  
D. R. BHASKAR ◽  
R. K. SHARMA

A number of configurations for realizing voltage-mode (VM) biquads using op-amps and OTAs have been presented in the literature, however, none of these provide the following desirable properties simultaneously: (i) realizability of all the five standard filters (namely; low pass, high pass, band pass, band stop and all pass), (ii) tunability of all the three filter parameters (namely; ω0, bandwidth or Q0 and gain) and (iii) not requiring any realization condition in any of the five filter responses. This paper presents a new configuration which does possess all the above mentioned desirable properties simultaneously while using only two internally-compensated type op-amps and a reasonable number of OTAs. The workability of the new configuration has been demonstrated by SPICE simulations based upon CMOS Op-amp and CMOS OTAs.


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