scholarly journals Comparison analysis of three value logic 8T CNTFET SRAM Cell with 6 CMOS SRAM CELL at 32nm technology

2019 ◽  
Vol 8 (2) ◽  
pp. 107
Author(s):  
S.Tamil Selvan
Keyword(s):  
Carbon Nanotube ◽  
Low Power ◽  
Power Dissipation ◽  
Gate Length ◽  
Comparison Analysis ◽  
Large Parameter ◽  
Exponential Increase ◽  
Sram Cell ◽  
Parameter Variations ◽  
Delay Increase

<p>This paper proposed a new concept of highly SNM and low power SRAM cell using carbon nanotube FETs (CNTFETs) at 18nm technology node. As device physical gate length is reduced to below 65 nm, device non-idealities such as large parameter variations and exponential increase in Dynamic leakage current make the I-V characteristics substantially different from traditional MOSFETs and become a serious obstacle to scale devices. CNFETs have received widespread attention as one of the promising successor to MOSFETs. The proposed circuit was simulated in HSPICE using 32nm Stanford CNFET model. Analysis of the results shows that the proposed CNTFET based 3VL 8T SRAM cell, power dissipation, and stability substantially improved compared with the conventional CMOS 6T SRAM cell by 51% and 58% respectively at the expense of 4% write delay increase.</p>

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

scholarly journals Comprehensive Analysis of SRAM Cell Architectures With 18nm FinFET for Low Power Applications

2021 ◽  
Author(s):  
T. Santosh Kumar ◽  
Suman Lata Tripathi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Reduction Technique ◽  
Leakage Currents ◽  
Leakage Reduction ◽  
Sram Cell ◽  
Supply Voltage Scaling ◽  
Better Than

Abstract The SRAM cells are used in many applications where power consumption will be the main constraint. The Conventional 6T SRAM cell has reduced stability and more power consumption when technology is scaled resulting in supply voltage scaling, so other alternative SRAM cells from 7T to 12T have been proposed which can address these problems. Here a low power 7T SRAM cell is suggested which has low power consumption and condensed leakage currents and power dissipation. The projected design has a leakage power of 5.31nW and leakage current of 7.58nA which is 84.9% less than the 7T SRAM cell without using the proposed leakage reduction technique and it is 22.4% better than 6T SRAM and 22.1% better than 8T SRAM cell when both use the same leakage reduction technique. The cell area of the 7T SRAM cell is 1.25µM2, 6T SRAM is 1.079µM2 and that of 8T SRAM is 1.28µM2all the results are simulated in cadence virtuoso using 18nm technology.

Performance limit of monolayer MoSi2N4 transistors

2021 ◽  
Author(s):  
Xiaotian Sun ◽  
Zhigang Song ◽  
Nannan Huo ◽  
Shiqi Liu ◽  
Chen Yang ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Gate Length ◽  
Performance Limit ◽  
Low Power Dissipation

The ultra-short gate-length ML MoSi2N4 MOSFET can meet the ITRS requirements with low power dissipation.

scholarly journals Robust 12T Sram Cell Using 45nm Technology

2020 ◽  
pp. 170-174
Author(s):  
N. Geetha Rani ◽  
N. Jyothi ◽  
P. Leelavathi ◽  
P. Deepthi Swarupa Rani ◽  
S. Reshma
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Leakage Power ◽  
Sram Cell ◽  
Static Power ◽  
Low Supply Voltage ◽  
Multi Core Processor

SRAM cells are used in many applications such as micro and multi core processor. SRAM cell improves both read stability and write ability at low supply voltage. The objective is to reduce the power dissipation of a novel low power 12T SRAM cell. This method removes half-select issue in 6T and 9T SRAM cell. This work proposes new functional low-power designs of SRAM cells with 6T, 9T and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. The leakage power consumption of the proposed SRAM cell is thereby reduced compared to that of the conventional six-transistor (6T) SRAM cell. 12T cell obtains low static power dissipation.

A New High Speed Low Power Dissipation Three-Element Si-Based SRAM Cell

2013 ◽  
Vol 52 (1) ◽  
pp. 105-109 ◽  
Author(s):  
X. Tong ◽  
H. Wu ◽  
L. Zhao ◽  
H. Zhong
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Sram Cell ◽  
Low Power Dissipation
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