Enhancement of the Retention Characteristics in Solution-Processed Ferroelectric Memory Transistor with Dual-Gate Structure

2021 ◽  
Vol 21 (3) ◽  
pp. 1766-1771
Author(s):  
Amos Amoako Boampong ◽  
Jae-Hyeok Cho ◽  
Yoonseuk Choi ◽  
Min-Hoi Kim
Keyword(s):  
High Performance ◽  
Thin Film Transistor ◽  
High Mobility ◽  
Ferroelectric Thin Film ◽  
Solution Processed ◽  
Gate Structure ◽  
Dual Gate ◽  
Retention Characteristics ◽  
Ferroelectric Memory ◽  
Bottom Gate

We demonstrated the enhancement of the retention characteristics in solution-processed ferroelectric memory transistors. For enhanced retention characteristics, solution-processed Indium Gallium Zinc Oxide (InGaZnO) semiconductor is used as an active layer in a dual-gate structure to achieve high memory on-current and low memory off-current respectively. In our dual-gate oxide ferroelectric thin-film transistor (DG Ox-FeTFT), while conventional TFT characteristic is observed during bottom-gate sweeping, large hysteresis is exhibited during top-gate sweeping with high memory on-current due to the high mobility of the InGaZnO. The voltage applied to the counter bottom-gate electrode causes variations in the turn-on voltage position, which controlled the memory on- and off-current in retention characteristics. Specifically, due to the full depletion of semiconductor by the high negative counter gate bias, the memory off-current in reading operation is dramatically reduced by 104. The application of a high negative counter field to the dual-gate solution-processed ferroelectric memory gives a high memory on- and off-current ratio useful for the production of high performance multi-bit memory devices.

Dual-Gate SiO2/P3HT/SiNx OTFT

2005 ◽  
Vol 871 ◽  
Author(s):  
Flora Li ◽  
Sarswati Koul ◽  
Yuri Vygranenko ◽  
Peyman Servati ◽  
Arokia Nathan
Keyword(s):  
Threshold Voltage ◽  
Gate Dielectric ◽  
Thin Film Transistor ◽  
Semiconductor Layer ◽  
Organic Thin Film ◽  
Active Matrix ◽  
Gate Structure ◽  
Active Matrix Displays ◽  
Dual Gate ◽  
Bottom Gate

AbstractThis paper reports on a new organic thin-film transistor (OTFT) based on a dual-gate configuration. This dual-gate OTFT is useful in circuit applications from the standpoint of providing control over selected device parameters for enhanced circuit reliability. Moreover, the dual-gate structure can shield parasitic effects in vertically integrated electronics, making it particularly promising for active matrix display and imaging applications. The dual-gate OTFT also lends itself as a highly functional test structure for characterization of interface integrity of the active organic and dielectric layers. In this work, the dual-gate OTFT is fabricated using regioregular poly(3-hexylthiophene) (P3HT) as the organic semiconductor layer. The bottom-gate employs silicon dioxide (SiO2) as the gate dielectric, whereas the top-gate employs a low-temperature amorphous silicon nitride (SiNx) as the passivation dielectric. The voltage on the bottom-gate has a distinct influence on the threshold voltage, subthreshold slope, on-current, and leakage current of the top-gate TFT. Similar dependence of the bottom-gate TFT characteristics on the top-gate voltage is observed. This design provides a means of characterizing the density of states of the bottom P3HT/SiO2 and top P3HT/SiNx interfaces, and conveys insight into the underlying transport mechanisms. The ability to control selected TFT parameters (e.g., threshold voltage) using the dual-gate OTFT structure is attractive for circuit integration applications in active matrix displays and imagers.

Indium–gallium–zinc–oxide thin-film transistor with a planar split dual-gate structure

2017 ◽  
Vol 31 (35) ◽  
pp. 1750332
Author(s):  
Yu-Rong Liu ◽  
Jie Liu ◽  
Jia-Qi Song ◽  
Pui-To Lai ◽  
Ruo-He Yao
Keyword(s):  
Thin Film ◽  
Zinc Oxide ◽  
Thin Film Transistor ◽  
Oxide Thin Film ◽  
Indium Gallium Zinc Oxide ◽  
Practical Applications ◽  
Gate Structure ◽  
Dual Gate ◽  
Indium Gallium ◽  
Output Characteristics

An amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistor (TFT) with a planar split dual gate (PSDG) structure has been proposed, fabricated and characterized. Experimental results indicate that the two independent gates can provide dynamical control of device characteristics such as threshold voltage, sub-threshold swing, off-state current and saturation current. The transconductance extracted from the output characteristics of the device increases from [Formula: see text] to [Formula: see text] for a change of control gate voltage from −2 V to 2 V, and thus the device could be used in a variable-gain amplifier. A significant advantage of the PSDG structure is its flexibility in controlling the device performance according to the need of practical applications.

High-Performance Solution-Processed InGaZnO Thin-Film Transistor Fabricated by Ozone-Assisted Atmospheric Pressure Mist Deposition

2014 ◽  
Vol 10 (11) ◽  
pp. 934-938 ◽  
Author(s):  
Mamoru Furuta ◽  
Toshiyuki Kawaharamura ◽  
Takayuki Uchida ◽  
Dapeng Wang ◽  
Masaru Sanada
Keyword(s):  
Thin Film ◽  
Atmospheric Pressure ◽  
High Performance ◽  
Thin Film Transistor ◽  
Solution Processed ◽  
Mist Deposition

scholarly journals High-performance, semiconducting membrane composed of ultrathin, single-crystal organic semiconductors

2019 ◽  
Vol 117 (1) ◽  
pp. 80-85 ◽  
Author(s):  
Tatsuyuki Makita ◽  
Shohei Kumagai ◽  
Akihito Kumamoto ◽  
Masato Mitani ◽  
Junto Tsurumi ◽  
...  
Keyword(s):  
Single Crystal ◽  
Organic Semiconductors ◽  
High Performance ◽  
Printed Electronics ◽  
Electronic Device ◽  
Molecular Layer ◽  
High Mobility ◽  
Building Blocks ◽  
Solution Processed ◽  
Transfer Method

Thin film transistors (TFTs) are indispensable building blocks in any electronic device and play vital roles in switching, processing, and transmitting electronic information. TFT fabrication processes inherently require the sequential deposition of metal, semiconductor, and dielectric layers and so on, which makes it difficult to achieve reliable production of highly integrated devices. The integration issues are more apparent in organic TFTs (OTFTs), particularly for solution-processed organic semiconductors due to limits on which underlayers are compatible with the printing technologies. We demonstrate a ground-breaking methodology to integrate an active, semiconducting layer of OTFTs. In this method, a solution-processed, semiconducting membrane composed of few-molecular-layer–thick single-crystal organic semiconductors is exfoliated by water as a self-standing ultrathin membrane on the water surface and then transferred directly to any given underlayer. The ultrathin, semiconducting membrane preserves its original single crystallinity, resulting in excellent electronic properties with a high mobility up to 12cm2⋅V−1⋅s−1. The ability to achieve transfer of wafer-scale single crystals with almost no deterioration of electrical properties means the present method is scalable. The demonstrations in this study show that the present transfer method can revolutionize printed electronics and constitute a key step forward in TFT fabrication processes.

High Performance Dual Gate Amorphous In-Ga-Zn-O Thin Film Transistor with Nanometer Dot-like Doping

2012 ◽  
Author(s):  
H. W. Zan ◽  
C. H. Liao ◽  
C. H. Li ◽  
C. C. Tsai ◽  
W. T. Chen ◽  
...  
Keyword(s):  
Thin Film ◽  
High Performance ◽  
Thin Film Transistor ◽  
Dual Gate

Pentacene Organic Thin-Film Transistors with Dual-Gate Structure

2007 ◽  
Vol 124-126 ◽  
pp. 383-386
Author(s):  
Jae Bon Koo ◽  
Jung Wook Lim ◽  
Chan Hoe Ku ◽  
Sang Chul Lim ◽  
Jung Hun Lee ◽  
...  
Keyword(s):  
Thin Film ◽  
Electrostatic Potential ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Atomic Layer ◽  
Organic Thin Film Transistors ◽  
Organic Thin Film ◽  
Gate Structure ◽  
Dual Gate ◽  
Bottom Gate

We report on the fabrication of dual-gate pentacene organic thin-film transistors (OTFTs) using a plasma-enhanced atomic layer deposited (PEALD) 150 nm thick Al2O3 as a bottom gate dielectric and a 300 nm thick parylene or a PEALD 200 nm thick Al2O3 as both a top gate dielectric and a passivation layer. The threshold voltage (Vth) of OTFT with a 300 nm thick parylene as a top gate dielectric is changed from 4.7 V to 1.3 V and that with a PEALD 200 nm thick Al2O3 as a top gate dielectric is changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode is changed from -10 V to 10 V. The change of Vth of OTFT with the dual-gate structure has been successfully understood by an analysis of electrostatic potential.

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