Case Study on Failure Analysis of Electrostatic Discharge Damage of Semiconductor Devices

Abstract This paper presents the failure analysis on a 1.5m flex harness for a space flight instrument that exhibited two failure modes: global isolation resistances between all adjacent traces measured tens of milliohm and lower resistance on the order of 1 kiloohm was observed on several pins. It shows a novel method using a temperature controlled air stream while monitoring isolation resistance to identify a general area of interest of a low isolation resistance failure. The paper explains how isolation resistance measurements were taken and details the steps taken in both destructive and non-destructive analyses. In theory, infrared hotspot could have been completed along the length of the flex harness to locate the failure site. However, with a field of view of approximately 5 x 5 cm, this technique would have been time prohibitive.

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Failure Analysis of CDM-ESD Damage in a GaAs RFIC

ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2000p0215 ◽

2000 ◽

Author(s):

Amy Poe ◽

Steve Brockett ◽

Tony Rubalcava

Keyword(s):

Radio Frequency ◽

Failure Analysis ◽

Integrated Circuit ◽

Production Test ◽

Analysis Techniques ◽

Device Model ◽

Charged Device ◽

Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

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Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0233 ◽

2010 ◽

Author(s):

Kuo Hsiung Chen ◽

Wen Sheng Wu ◽

Yu Hsiang Shu ◽

Jian Chan Lin

Keyword(s):

Failure Analysis ◽

Failure Mechanisms ◽

Fault Localization ◽

Resistance Change ◽

The Real ◽

Analysis Techniques ◽

Analysis Technique ◽

Leakage Failure ◽

Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

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The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage

ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2006p0257 ◽

2006 ◽

Author(s):

Tsung-Te Li ◽

Chao-Chi Wu ◽

Jung-Hsiang Chuang ◽

Jon C. Lee

Keyword(s):

Failure Analysis ◽

Electrical Characterization ◽

Physical Analysis ◽

Gate Leakage ◽

Force Microscopy ◽

Atomic Force ◽

Transmission Electron ◽

Voltage Stress ◽

Leakage Site

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

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A Novel Junction Profiling Methodology

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0171 ◽

2010 ◽

Author(s):

Tomokazu Nakai

Keyword(s):

Failure Analysis ◽

Profile Analysis ◽

Semiconductor Devices ◽

Wet Etching ◽

Two Dimensional ◽

Electrical Characteristics ◽

Conventional Methods

Abstract Currently many methods are available to obtain a junction profile of semiconductor devices, but the conventional methods have drawbacks, and they could be obstacles for junction profile analysis. This paper introduces an anodic wet etching-based two-dimensional junction profiling method, which is practical, efficient, and reliable for failure analysis and electrical characteristics evaluation.

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Case Study in Fault Isolation of a Metal Short for Yield Enhancement

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0049 ◽

2010 ◽

Author(s):

Sarven Ipek ◽

David Grosjean

Keyword(s):

Failure Analysis ◽

Failure Mechanism ◽

Photon Emission ◽

Fault Isolation ◽

Yield Enhancement ◽

Analysis Technique ◽

Laser Signal ◽

Signal Injection ◽

Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

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A Methodology for Characterizing System-Level ESD Sensitivity

ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2004p0277 ◽

2004 ◽

Author(s):

Marie-Pascale Chagny ◽

John A. Naoum

Keyword(s):

Electrostatic Discharge ◽

Computer Systems ◽

Electronic Equipment ◽

Experimental Methodology ◽

Computer Users ◽

System Level ◽

Permanent Damage ◽

Design Improvement ◽

Desktop Computers

Abstract Over the years, failures induced by an electrostatic discharge (ESD) have become a major concern for semiconductor manufacturers and electronic equipment makers. The ESD events that cause destructive failures have been studied extensively [1, 2]. However, not all ESD events cause permanent damage. Some events lead to recoverable failures that disrupt system functionality only temporarily (e.g. reboot, lockup, and loss of data). These recoverable failures are not as well understood as the ones causing permanent damage and tend to be ignored in the ESD literature [3, 4]. This paper analyzes and characterizes how these recoverable failures affect computer systems. An experimental methodology is developed to characterize the sensitivity of motherboards to ESD by simulating the systemlevel ESD events induced by computer users. The manuscript presents a case study where this methodology was used to evaluate the robustness of desktop computers to ESD. The method helped isolate several weak nets contributing to the failures and identified a design improvement. The result was that the robustness of the systems improved by a factor of 2.

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Reballing/Rebumping Ultra-Fine Pitch Packages Less Than 0.5 mm Pitch for FA

ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2014p0160 ◽

2014 ◽

Author(s):

Bob Wettermann

Keyword(s):

Solder Joint ◽

Failure Analysis ◽

Joint Strength ◽

Semiconductor Devices ◽

X Ray ◽

Fine Pitch ◽

Manual Methods

Abstract As the pitch and package sizes of semiconductor devices have shrunk and their complexity has increased, the manual methods by which the packages can be re-bumped or reballed for failure analysis have not kept up with this miniaturization. There are some changes in the types of reballing preforms used in these manual methods along with solder excavation techniques required for packages with pitches as fine as 0.3mm. This paper will describe the shortcomings of the previous methods, explain the newer methods and materials and demonstrate their robustness through yield, mechanical solder joint strength and x-ray analysis.

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Die-Level Scanning Capacitance Microscopy Fault Isolation on SOI Fin-FET Devices for Advanced Semiconductor Nodes

10.31399/asm.cp.istfa2018p0543 ◽

2018 ◽

Author(s):

Lucile C. Teague Sheridan ◽

Tanya Schaeffer ◽

Yuting Wei ◽

Satish Kodali ◽

Chong Khiam Oh

Keyword(s):

Atomic Force Microscopy ◽

Failure Analysis ◽

Fault Isolation ◽

Scanning Capacitance Microscopy ◽

Force Microscopy ◽

Atomic Force

Abstract It is widely acknowledged that Atomic force microscopy (AFM) methods such as conductive probe AFM (CAFM) and Scanning Capacitance Microscopy (SCM) are valuable tools for semiconductor failure analysis. One of the main advantages of these techniques is the ability to provide localized, die-level fault isolation over an area of several microns much faster than conventional nanoprobing methods. SCM, has advantages over CAFM in that it is not limited to bulk technologies and can be utilized for fault isolation on SOI-based technologies. Herein, we present a case-study of SCM die-level fault isolation on SOI-based FinFET technology at the 14nm node.

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