Optimization of Wireless Transceivers under Processing Energy Constraints

Frequenz ◽  
2017 ◽  
Vol 71 (9-10) ◽  
pp. 379-388
Author(s):  
Gaojian Wang ◽  
Gerd Ascheid ◽  
Yanlu Wang ◽  
Oner Hanay ◽  
Renato Negra ◽  
...  

Abstract Focus of the article is on achieving maximum data rates under a processing energy constraint. For a given amount of processing energy per information bit, the overall power consumption increases with the data rate. When targeting data rates beyond 100 Gb/s, the system’s overall power consumption soon exceeds the power which can be dissipated without forced cooling. To achieve a maximum data rate under this power constraint, the processing energy per information bit must be minimized. Therefore, in this article, suitable processing efficient transmission schemes together with energy efficient architectures and their implementations are investigated in a true cross-layer approach. Target use cases are short range wireless transmitters working at carrier frequencies around 60 GHz and bandwidths between 1 GHz and 10 GHz.

2012 ◽  
Vol 47 (7) ◽  
pp. 1743-1756 ◽  
Author(s):  
Jonathan Muller ◽  
Bruno Stefanelli ◽  
Antoine Frappe ◽  
Lu Ye ◽  
Andreia Cathelin ◽  
...  

2011 ◽  
Vol 3 (2) ◽  
pp. 139-145 ◽  
Author(s):  
Srdjan Glisic ◽  
J. Christoph Scheytt ◽  
Yaoming Sun ◽  
Frank Herzel ◽  
Ruoyu Wang ◽  
...  

A fully integrated transmitter (TX) and receiver (RX) front-end chipset, produced in 0.25 µm SiGe:C bipolar and complementary metal oxide semiconductor (BiCMOS) technology, is presented. The front-end is intended for high-speed wireless communication in the unlicensed ISM band of 9 GHz around 60 GHz. The TXand RX features a modified heterodyne topology with a sliding intermediate frequency. The TX features a 12 GHz in-phase and quadrature (I/Q) mixer, an intermediate frequency (IF) amplifier, a phase-locked loop, a 60 GHz mixer, an image-rejection filter, and a power amplifier. The RX features a low-noise amplifier (LNA), a 60 GHz mixer, a phase-locked loop (PLL), and an IF demodulator. The measured 1-dB compression point at the TX output is 12.6 dBm and the saturated power is 16.2 dBm. The LNA has measured noise figure of 6.5 dB at 60 GHz. Error-free data transmission with a 16 quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal and data rate of 3.6 Gbit/s (without coding 4.8 Gbit/s) over 15 m was demonstrated. This is the best reported result regarding both the data rate and transmission distance in SiGe and CMOS without beamforming.


2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.


2018 ◽  
Vol 7 (4) ◽  
pp. 2569
Author(s):  
Priyanka Chauhan ◽  
Dippal Israni ◽  
Karan Jasani ◽  
Ashwin Makwana

Data acquisition is the most demanding application for the acquisition and monitoring of various sensor signals. The data received are processed in real-time environment. This paper proposes a novel Data Acquisition (DAQ) technique for better resource utilization with less power consumption. Present work has designed and compared advanced Quad Data Rate (QDR) technique with traditional Dual Data Rate (DDR) technique in terms of resource utilization and power consumption of Field Programmable Gate Array (FPGA) hardware. Xilinx ISE is used to verify results of FPGA resource utilization by QDR with state of the art DDR approach. The paper ratiocinates that QDR technique outperforms traditional DDR technique in terms of FPGA resource utilization.  


2013 ◽  
Vol 9 (3) ◽  
pp. 170 ◽  
Author(s):  
Nyoman Gunantara ◽  
Gamantyo Hendrantoro

This paper focuses in the selection of an optimal path pair for cooperative diversity based on cross-layer optimization in multihop wireless ad hoc networks. Cross-layer performance indicators, including power consumption, signal-to-noise ratio, and load variance are optimized using multi-objective optimization (MOO) with Pareto method. Consequently, optimization can be performed simultaneously to obtain a compromise among three resources over all possible path pairs. The Pareto method is further compared to the scalarization method in achieving fairness to each resource. We examine the statistics of power consumption, SNR, and load variance for both methods through simulations. In addition, the complexity of the optimization of both methods is evaluated based on the required computing time.


Author(s):  
Archana B. ◽  
T. P. Surekha

The growing interest towards wireless communication advancement with smart devices has provided the desired throughput of wireless communication mechanisms. But, attaining high-speed data packets amenities is the biggest issue in different multimedia applications. Recently, OFDM has come up with the useful features for wireless communication however it faces interference issues at carrier level (intercarrier interferences). To resolve these interference issues in OFDM, various existing mechanisms were utilized cyclic prefix, but it leads to redundancy in transmitted data. Also, the transmission of this redundant data can take some more power and bandwidth. All these limitations factors can be removed from a parallel cancellation mechanism. The integration of parallel cancellation and Convolution Viterbi encoding and decoding in MIMO-OFDMA will be an effective solution to have high data rate which also associations with the benefits of both the architectures of MIMO and OFDMA modulation approaches. This paper deals with this integrated mechanism for efficient resource allocation and power consumption. For performance analysis, MIMO-OFDMA system is analyzed with three different approaches likeMIMO-OFDM system without parallel cancellation (MIMO-OFDMA-WPC), MIMO-OFDMA System with parallel cancellation (MIMO-OFDMA-PC) and proposed IMO-OFDMA system with parallel cancellation and Convolution Viterbi encoding/decoding (pMIMO-OFDMA-PC &CVed) for 4x4 transmitter and receiver. Through performance analysis, it is found that the proposed system achieved better resource allocation (bandwidth) with high data rate by minimized BER rate and achieved least power consumption with least BER.


2010 ◽  
Vol 28 (16) ◽  
pp. 2296-2306 ◽  
Author(s):  
Chun-Ting Lin ◽  
Jyehong Chen ◽  
Po-Tsung Shih ◽  
Wen-Jr Jiang ◽  
Sien Chi

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