Patterned wafers backside thinning for 3-D Integration and multilayer stack achievement by direct wafer bonding

2008 ◽  
Vol 1079 ◽  
Author(s):  
Barbara Charlet ◽  
Antoine Chiteboun ◽  
Marc Zussy ◽  
Laurent Bally ◽  
Patrick Leduc ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
3D Structure ◽  
Wafer Level ◽  
3D Integration ◽  
Patterned Substrate ◽  
Patterned Wafers ◽  
Direct Wafer Bonding ◽  
Scaling Down ◽  
Silicon Thickness ◽  
Wafer Thinning

ABSTRACTScaling down the devices to keep increasing the integrated circuits (ICs) performance at the rate defined by Moore's [1] law becomes more and more difficult and so costly that new circuits architectures and new integration technologies are investigated. One of the most promising ways in integration technology is the vertical stacking of circuits, also called “3D Integration”. One of the challenges in this technology is the patterned substrate backside thinning. Compatibility with the whole 3D Integration process has to be guaranteed, the existing circuit has to be kept intact and the bonding interface mustn't be damaged. In this study we discuss some experimental results of wafer thinning by grinding and polishing of molecular bonded silicon wafers applied to 3D Integration [2-4]. The wafer with patterned copper interconnections are stacked by direct SiO2 bonding and thinned down on one backside. These stacks are then bonded again to one or two circuits via a deposited oxide on the thinned surface. The top bulk Si surface was thinned down again on one backside, giving a multi layers stack. This wafer level vertical assembly demonstrates the possibility to adjust the remaining Silicon thickness to small values (<15μm) and then bond the thinned surface to achieve multiple layer 3D structure.

Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

2004 ◽  
Vol 816 ◽  
Author(s):  
J.-Q. Lu ◽  
G. Rajagopalan ◽  
M. Gupta ◽  
T.S. Cale ◽  
R.J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
3D Integration ◽  
Edge Chipping ◽  
3D Ics ◽  
Process Compatibility ◽  
Wafer Thinning ◽  
Thinning Process

AbstractMonolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

Fundamental Limits for 3D Wafer-to-Wafer Alignment Accuracy

2004 ◽  
Vol 812 ◽  
Author(s):  
M. Wimplinger ◽  
J.-Q. Lu ◽  
J. Yu ◽  
Y. Kwon ◽  
T. Matthias ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Alignment Accuracy ◽  
Wafer Level ◽  
3D Integration ◽  
3D Technology ◽  
Fundamental Limits ◽  
Technology Platforms ◽  
Global Interconnects ◽  
Wafer Thinning ◽  
Alternative Alignment

AbstractWafer-level three-dimensional (3D) integration as an emerging architecture for future chips offers high interconnect performance by reducing delays of global interconnects and high functionality with heterogeneous integration of materials, devices, and signals. Various 3D technology platforms have been investigated, with different combinations of alternative alignment, bonding, thinning and inter-wafer interconnection technologies. Precise alignment on the wafer level is one of the key challenges affecting the performance of the 3D interconnects. After a brief overview of the wafer-level 3D technology platforms, this paper focuses on waferto-wafer alignment fundamentals. Various alignment methods are reviewed. A higher emphasis lies on the analysis of the alignment accuracy. In addition to the alignment accuracy achieved prior to bonding, the impacts of wafer bonding and subsequent wafer thinning will be discussed.

Electrical Invasiveness of Grinding and Polishing Silicon Integrated Circuits Down to 1 μm Remaining Silicon Thickness

2016 ◽  
Author(s):  
Robert Chivas ◽  
Scott Silverman ◽  
Michael DiBattista ◽  
Ulrike Kindereit
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Electron Hole ◽  
Analysis Techniques ◽  
Silicon Integrated Circuits ◽  
Electron Hole Pair ◽  
Pair Generation ◽  
Silicon Thickness ◽  
Performance Timing ◽  
Grinding And Polishing

Abstract Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to electron-hole pair generation. In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (&lt; 5 um global, ~ 1 um local) remaining thickness is presented.

High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing

2016 ◽  
Vol 75 (9) ◽  
pp. 345-353 ◽  
Author(s):  
F. Kurz ◽  
T. Plach ◽  
J. Suss ◽  
T. Wagenleitner ◽  
D. Zinner ◽  
...  
Keyword(s):  
Low Temperature ◽  
High Precision ◽  
Wafer Bonding ◽  
Wafer Level ◽  
3D Ics ◽  
Direct Wafer Bonding ◽  
Bonding Technology

Wafer Thinning Solution for Wafer-Level-Capped MEMS Devices

2006 ◽  
Author(s):  
E.S. Lacsamana ◽  
M.G. Mena ◽  
R.M. Navarro ◽  
N. Kuan ◽  
T.R. Spooner
Keyword(s):  
Mems Devices ◽  
Wafer Level ◽  
Wafer Thinning

Single-Crystalline and Bamboo Al Lines Fabricated by Graphoepitaxy: Microstructure and 1/f Noise Measurements

1996 ◽  
Vol 428 ◽  
Author(s):  
Marc J.C. Van Den Homberg ◽  
A. H. Verbruggen ◽  
P. F. A. Alkemade ◽  
S. Radelaar
Keyword(s):  
Integrated Circuits ◽  
Grain Boundaries ◽  
Low Noise ◽  
Dc Magnetron Sputtering ◽  
Rapid Thermal Anneal ◽  
Single Crystalline ◽  
Noise Measurements ◽  
Scaling Down ◽  
Sputter Deposited

AbstractThe continuing scaling-down of integrated circuits leads to increased metallization reliability problems, especially electromigration. We used 1/f noise measurements to study the relation between electromigration and microstructure. These measurements are very sensitive to the microstructural attributes, such as grain boundaries and dislocations. Al lines were grown by graphoepitaxy: First, a pure Al film was grown by dc magnetron sputtering on a groove pattern etched into a SiO2 substrate. The growth was then followed by an in situ rapid thermal anneal that resulted in a complete filling of the grooves with Al. These Al lines were carefully characterized with SEM and Backscatter Kikuchi Diffraction. Depending on the presence of a temperature gradient during the anneal, the lines were either nearly single-crystalline or bamboo with one grain per ∼ 3 μm. The resistivity was ∼ 2.8 μΩcm, only slightly higher than for bulk Al. We measured the 1/f noise with the two-channel ac technique at RT. We found in both bamboo as well as the single-crystalline lines a very low noise intensity; a factor two lower than in conventionally sputter deposited and annealed Al lines. No clear difference between the noise spectra of the bamboo and the single-crystalline lines was observed. We concluded that grain boundaries are not the only contributor to 1/f noise; other types of defects must play a role as well.

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