Fundamental Limits for 3D Wafer-to-Wafer Alignment Accuracy

2004 ◽  
Vol 812 ◽  
Author(s):  
M. Wimplinger ◽  
J.-Q. Lu ◽  
J. Yu ◽  
Y. Kwon ◽  
T. Matthias ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Alignment Accuracy ◽  
Wafer Level ◽  
3D Integration ◽  
3D Technology ◽  
Fundamental Limits ◽  
Technology Platforms ◽  
Global Interconnects ◽  
Wafer Thinning ◽  
Alternative Alignment

AbstractWafer-level three-dimensional (3D) integration as an emerging architecture for future chips offers high interconnect performance by reducing delays of global interconnects and high functionality with heterogeneous integration of materials, devices, and signals. Various 3D technology platforms have been investigated, with different combinations of alternative alignment, bonding, thinning and inter-wafer interconnection technologies. Precise alignment on the wafer level is one of the key challenges affecting the performance of the 3D interconnects. After a brief overview of the wafer-level 3D technology platforms, this paper focuses on waferto-wafer alignment fundamentals. Various alignment methods are reviewed. A higher emphasis lies on the analysis of the alignment accuracy. In addition to the alignment accuracy achieved prior to bonding, the impacts of wafer bonding and subsequent wafer thinning will be discussed.

Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

2004 ◽  
Vol 816 ◽  
Author(s):  
J.-Q. Lu ◽  
G. Rajagopalan ◽  
M. Gupta ◽  
T.S. Cale ◽  
R.J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
3D Integration ◽  
Edge Chipping ◽  
3D Ics ◽  
Process Compatibility ◽  
Wafer Thinning ◽  
Thinning Process

AbstractMonolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

Die-on-Wafer and Wafer-Level Three-Dimensional (3D) Integration of Heterogeneous IC Technologies for RF-Microwave-Millimeter Applications

2004 ◽  
Vol 833 ◽  
Author(s):  
J.-Q. Lu ◽  
S. Devarajan ◽  
A. Y. Zeng ◽  
K. Rose ◽  
R. J. Gutmann
Keyword(s):  
High Performance ◽  
Three Dimensional ◽  
Wafer Level ◽  
3D Integration ◽  
3D Technology ◽  
Passive Components ◽  
Analog To Digital ◽  
Integration Platform ◽  
Rf Transceivers ◽  
Rf Microwave

ABSTRACTDie-on-wafer and wafer-level three-dimensional (3D) integrations of heterogeneous IC technologies are briefly described, emphasizing a specific 3D hyper-integration platform using dielectric adhesive wafer bonding and Cu damascene inter-wafer interconnects to provide a perspective on wafer-level 3D technology processing. Wafer-level 3D partitioning of high Q passive components, analog-to-digital (A/D) converters, RF transceivers, digital processors, and memory is discussed for high-performance RF-microwave-millimeter applications, especially where high manufacturing quantities are anticipated. Design and simulation results of 3D heterogeneous integration are presented. This 3D technology is applicable to smart wireless terminals, millimeter phased array radars, and smart imagers.

Global Planarization Requirements for Wafer-Level Three-Dimensional (3D) ICs

2005 ◽  
Author(s):  
R. J. Gutmann ◽  
J. J. McMahon ◽  
J.-Q. Lu
Keyword(s):  
Integrated Circuit ◽  
Thermal Processing ◽  
Three Dimensional ◽  
Wafer Level ◽  
3D Integration ◽  
3D Ics ◽  
Technology Platforms ◽  
Technology Focus ◽  
Feature Scale ◽  
Ic Technology

Planarization needs for integrated circuit (IC) technology focus on feature-scale (100nm–1μm) and die-scale (5mm-20mm) dimensions. As three-dimensional (3D) integration moves from die-by-die assembly to wafer-level integration to provide a higher density of low electrical parasitic vertical interconnects (or vias), wafer-level planarization needs to be considered. Planarization needs depend upon the 3D technology platform approach (such as (1) blanket bonding followed by inter-wafer interconnect processing or via-first processing followed by bonding and thinning to expose the vias and (2) the number of wafers in a 3D stack) and the processing conditions used in fabricating the wafers to be 3D integrated (in particular, the built-in stress levels and post-bonding thermal processing budget). This invited presentation includes a summary of the current interest in wafer-level 3D integration in both the academic and industrial research community. Wafer-level planarization issues with different technology platforms are presented, and the limited results presented in the literature to date are summarized. The importance of wafer-level planarization compared to bonding, thinning and wafer-to-wafer alignment is discussed.

CMP Compatibility of Partially Cured Benzocyclobutene (BCB) for a Via-First 3D IC Process

2005 ◽  
Vol 867 ◽  
Author(s):  
J. J. McMahon ◽  
F. Niklaus ◽  
R. J. Kumar ◽  
J. Yu ◽  
J.Q. Lu ◽  
...  
Keyword(s):  
High Performance ◽  
Removal Rate ◽  
Three Dimensional ◽  
Surface Damage ◽  
Wafer Level ◽  
Razor Blade ◽  
3D Ic ◽  
3D Technology ◽  
Process Step ◽  
Wide Range

AbstractWafer-level three dimensional (3D) IC technology offers the promise of decreasing RC delays by reducing long interconnect lines in high performance ICs. This paper focuses on a viafirst 3D IC platform, which utilizes a back-end-of-line (BEOL) compatible damascene-patterned layer of copper and Benzocyclobutene (BCB). This damascene-patterned copper/BCB serves as a redistribution layer between two fully fabricated wafer sets of ICs and offers the potential of high bonding strength and low contact resistance for inter-wafer interconnects between the wafer pair. The process would thus combine the electrical advantages of 3D technology using Cu-to-Cu bonding with the mechanical advantages of 3D technology using BCB-to-BCB bonding.In this work, partially cured BCB has been evaluated for copper damascene patterning using commercially available CMP slurries as a key process step for a via-first 3D process flow. BCB is spin-cast on 200 mm wafers and cured at temperatures ranging from 190°C to 250°C, providing a wide range of crosslink percentage. These films are evaluated for CMP removal rate, surface damage (surface scratching and embedded abrasives), and planarity with commercially available copper CMP slurries. Under baseline process parameters, erosion, and roughness changes are presented for single-level damascene test patterns. After wafers are bonded under controlled temperature and pressure, the bonding interface is inspected optically using glass-to-silicon bonded wafers, and the bond strength is evaluated by a razor blade test.

Patterned wafers backside thinning for 3-D Integration and multilayer stack achievement by direct wafer bonding

2008 ◽  
Vol 1079 ◽  
Author(s):  
Barbara Charlet ◽  
Antoine Chiteboun ◽  
Marc Zussy ◽  
Laurent Bally ◽  
Patrick Leduc ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
3D Structure ◽  
Wafer Level ◽  
3D Integration ◽  
Patterned Substrate ◽  
Patterned Wafers ◽  
Direct Wafer Bonding ◽  
Scaling Down ◽  
Silicon Thickness ◽  
Wafer Thinning

ABSTRACTScaling down the devices to keep increasing the integrated circuits (ICs) performance at the rate defined by Moore's [1] law becomes more and more difficult and so costly that new circuits architectures and new integration technologies are investigated. One of the most promising ways in integration technology is the vertical stacking of circuits, also called “3D Integration”. One of the challenges in this technology is the patterned substrate backside thinning. Compatibility with the whole 3D Integration process has to be guaranteed, the existing circuit has to be kept intact and the bonding interface mustn't be damaged. In this study we discuss some experimental results of wafer thinning by grinding and polishing of molecular bonded silicon wafers applied to 3D Integration [2-4]. The wafer with patterned copper interconnections are stacked by direct SiO2 bonding and thinned down on one backside. These stacks are then bonded again to one or two circuits via a deposited oxide on the thinned surface. The top bulk Si surface was thinned down again on one backside, giving a multi layers stack. This wafer level vertical assembly demonstrates the possibility to adjust the remaining Silicon thickness to small values (<15μm) and then bond the thinned surface to achieve multiple layer 3D structure.

scholarly journals Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1586
Author(s):  
Zhong Fang ◽  
Peng You ◽  
Yijie Jia ◽  
Xuchao Pan ◽  
Yunlei Shi ◽  
...  
Keyword(s):  
Adhesive Bonding ◽  
Low Cost ◽  
Three Dimensional ◽  
System Level ◽  
Process Conditions ◽  
Wafer Level ◽  
3D Integration ◽  
Bonding Pressure ◽  
Curing Conditions ◽  
Integration Technology

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si–Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

Dielectric GlueWafer Bonding For 3D ICs

2003 ◽  
Vol 766 ◽  
Author(s):  
Y. Kwon ◽  
A. Jinda ◽  
J.J. McMahon ◽  
J.Q. Lu ◽  
R.J. Gutmann ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Bonding Strength ◽  
Three Dimensional ◽  
Wafer Level ◽  
Four Point Bending ◽  
Mechanical And Electrical Properties ◽  
3D Ics ◽  
Bond Interface ◽  
Three Dimensional Integrated Circuit ◽  
Wafer Thinning

AbstractA process to bond 200 mm wafers for wafer-level three-dimensional integrated circuit (3D-IC) applications is discussed. Four-point bending is used to quantify the bonding strength and identify the weak interface. Using benzocylcobutene (BCB) glue, the bonding strength depends on (1) glue thickness, (2) glue film preparation, and (3) materials and structures on the wafer(s). A seamless BCB-to-BCB bond interface provides the highest bonding strength compared to other interfaces in these structures (> 34 J/m2). Mechanical and electrical properties of a wafer with copper interconnect structures are preserved after wafer bonding and wafer thinning, confirming the potential of the bonding process for 3D ICs.

Light-Induced Capacitance Alteration for Nondestructive Fault Isolation in TSV Structures for 3D Integration

2016 ◽  
Author(s):  
K.J.P. Jacobs ◽  
A. Khaled ◽  
M. Stucchi ◽  
T. Wang ◽  
M. Gonzalez ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Fault Isolation ◽  
Signal Generation ◽  
Wafer Level ◽  
3D Integration ◽  
Scanning Optical Microscopy ◽  
Voltage Contrast ◽  
Non Destructive ◽  
Electrical Connectivity ◽  
Scanning Electron

Abstract We report on a new non-destructive electrical fault isolation (EFI) technique to localize interconnection failures in through-silicon via (TSV) structures for three-dimensional (3-D) integration. The scanning optical microscopy (SOM) technique is based on light-induced capacitance alteration (LICA) and uses localized photon probing of TSV interconnect capacitance to localize interruptions of electrical connectivity. The technique is applicable to passivated devices and allows rapid, efficient, and non-destructive fault isolation at wafer level. We describe the physics behind signal generation of the technique and demonstrate the TSV photocapacitance effect. We further demonstrate the LICA technique on open failed TSV daisy chain structures and confirm our results with microprobing and voltage contrast measurements in a scanning electron microscope (SEM).

Fine Keyed Alignment and Bonding for Wafer-Level 3D ICs

2006 ◽  
Vol 914 ◽  
Author(s):  
Sang Hwui Lee ◽  
Frank Niklaus ◽  
J. Jay McMahon ◽  
Jian Yu ◽  
Ravi J. Kumar ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
State Of The Art ◽  
Three Dimensional ◽  
Alignment Accuracy ◽  
Wafer Level ◽  
Alignment Procedure ◽  
3D Ics ◽  
Side Walls ◽  
The One ◽  
Wafer Surfaces

AbstractPrecise wafer-to-wafer alignment accuracy is crucial to interconnecting circuits on different wafers in three dimensional integrated circuits. We discuss the use of fabricated structures on wafer surfaces to mechanically achieve higher alignment accuracy than can be achieved with our existing (baseline) alignment protocol. The keyed alignment structures rely on structures with tapered side-walls that can slide into each after two wafers are “pre-aligned” using our baseline alignment protocol. Results indicate that alignment accuracy is about a quarter micron, well below the one micron alignment accuracy obtained in our baseline alignment procedure using commercial state-of-the-art wafer alignment equipment. In addition to improving alignment, the alignment structures also hinder undesirable bonding-induced misalignment. The keyed alignment structures are also promising for nano-imprint lithography.

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