Contact Resistance and Methods for its Determination

1982 ◽  
Vol 18 ◽  
Author(s):  
S. Simon Cohen
Keyword(s):  
Integrated Circuits ◽  
Contact Resistance ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Vlsi Circuits ◽  
Single Element ◽  
Large Scale Integration ◽  
Proper Definition ◽  
Definition Of ◽  
Scale Integration

The problem of low resistance ohmic contacts to silicon has been of considerable technological interest. In recent years this problem has received special attention owing to the effect of scaling in very-large-scale integration (VLSI) technology. The field of ohmic contacts to semiconductors comprises two independent parts. First there exists the material science aspect. The choice of a suitable metallization system, the proper semiconductor parameters and the method of the contact formation is not obvious. Then there is the question of the proper definition of the contact resistance and the way it is measured.Several methods for contact resistance determination have been introduced in the past. All seem to have some drawbacks that either limit their usefulness or raise doubts as to their validity in certain situations. We shall discuss the two-, three- and four-terminal resistor methods of measurement. Relevant theoretical considerations will also be included.For conventional integrated circuits with a moderate junction depth of 1–2 μm, aluminum is uniquely suited as a single-element metallization system. However, for VLSI applications it may become obsolete because of several well-defined metallurgical problems. Thus, other metallization systems have to be investigated. We shall briefly discuss some recent data on several other metallization systems. Finally, the problem of size effects on the contact resistance will be discussed. Recent experimental results suggest important clues regarding the development of alternative metallization systems for VLSI circuits and also point to revisions of estimates of achievable design rules.

Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing

MRS Bulletin ◽  
1993 ◽  
Vol 18 (6) ◽  
pp. 46-51 ◽  
Author(s):  
S.P. Murarka ◽  
J. Steigerwald ◽  
R.J. Gutmann
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Access Time ◽  
Gigascale Integration ◽  
Interlayer Dielectric ◽  
Application Specific Integrated Circuits ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Application Specific

Continuing advances in the fields of very-large-scale integration (VLSI), ultralarge-scale integration (ULSI), and gigascale integration (GSI), leading to the continuing development of smaller and smaller devices, have continually challenged the fields of materials, processes, and circuit designs. The existing metallization schemes for ohmic contacts, gate metal, and interconnections are inadequate for the ULSI and GSI era. An added concern is the reliability of aluminum and its alloys as the current carrier. Also, the higher resistivity of Al and its use in two-dimensional networks have been considered inadequate, since they lead to unacceptably high values of the so-called interconnection delay or RC delay, especially in microprocessors and application-specific integrated circuits (ICs). Here, R refers to the resistance of the interconnection and C to the total capacitance associated with the interlayer dielectric. For the fastest devices currently available and faster ones of the future, the RC delay must be reduced to such a level that the contribution of RC to switching delays (access time) becomes a small fraction of the total, which is a sum of the inherent device delay associated with the semiconductor, the device geometry and type, and the RC delay.

scholarly journals Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits

2017 ◽  
Author(s):  
Vinícius Dos Santos Livramento ◽  
José Luís Güntzel
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
Consumer Electronics ◽  
Clock Frequency ◽  
Wide Range ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration

The evolution of CMOS technology made possible integrated circuits with billions of transistors assembled into a single silicon chip, giving rise to the jargon Very-Large-Scale Integration (VLSI). VLSI circuits span a wide range class of applications, including Application Specific Circuits and Systems-On-Chip. The latter are responsible for fueling the consumer electronics market, especially in the segment of smartphones and tablets, which are responsible for pushing hardware performance requirements every new generation. The required clock frequency affects the performance of a VLSI circuit and induces timing constraints that must be properly handled by synthesis tools. This thesis focuses on techniques for timing closure of cellbased VLSI circuits, i.e. techniques able to iteratively reduce the number of timing violations until the synthesis of the synchronous digital system reaches the specified target frequency.

scholarly journals Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4771
Author(s):  
Hyunyul Lim ◽  
Minho Cheong ◽  
Sungho Kang
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Large Scale ◽  
Vlsi Circuits ◽  
Wireless Sensor ◽  
Large Scale Integration ◽  
Diagnosis Method ◽  
Diagnosis Accuracy ◽  
Scan Chain ◽  
Scale Integration

Scan structures, which are widely used in cryptographic circuits for wireless sensor networks applications, are essential for testing very-large-scale integration (VLSI) circuits. Faults in cryptographic circuits can be effectively screened out by improving testability and test coverage using a scan structure. Additionally, scan testing contributes to yield improvement by identifying fault locations. However, faults in circuits cannot be tested when a fault occurs in the scan structure. Moreover, various defects occurring early in the manufacturing process are expressed as faults of scan chains. Therefore, scan-chain diagnosis is crucial. However, it is difficult to obtain a sufficiently high diagnosis resolution and accuracy through the conventional scan-chain diagnosis. Therefore, this article proposes a novel scan-chain diagnosis method using regression and fan-in and fan-out filters that require shorter training and diagnosis times than existing scan-chain diagnoses do. The fan-in and fan-out filters, generated using a circuit logic structure, can highlight important features and remove unnecessary features from raw failure vectors, thereby converting the raw failure vectors to fan-in and fan-out vectors without compromising the diagnosis accuracy. Experimental results confirm that the proposed scan-chain-diagnosis method can efficiently provide higher resolutions and accuracies with shorter training and diagnosis times.

Recent Progress of Alloyed Ohmic Contacts to GaAs Compound Semiconductors

1992 ◽  
Vol 260 ◽  
Author(s):  
Masanori Murakami ◽  
A. Otsuki ◽  
K. Tanahashi ◽  
H. J. Tarata ◽  
A. Callegari ◽  
...  
Keyword(s):  
Large Scale ◽  
Ohmic Contacts ◽  
Recent Progress ◽  
Excellent Thermal Stability ◽  
The Poor ◽  
Gaas Devices ◽  
Large Scale Integration ◽  
Smooth Contact ◽  
Scale Integration ◽  
Integration Levels

ABSTRACTLow resistance, alloyed AuGeNi Ohmic contacts have been extensively used in the current manufacturing GaAs devices. However, extension of usage of these devices to Very Large Scale Integration levels requires the contacts with excellent thermal stability, shallow diffusion depth, and smooth contact surface in addition to low contact resistance. In the present paper recent studies for development of “non-gold” Ohmic contacts which improve the poor contact properties of the alloyed Ohmic contacts are rev i ewed.

scholarly journals Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method

2021 ◽  
Vol 9 (VI) ◽  
pp. 962-966
Author(s):  
Ayush Tiwari
Keyword(s):  
Large Scale ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Time Duration ◽  
Leakage Reduction ◽  
Large Scale Integration ◽  
Cmos Vlsi ◽  
Scale Integration

Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits based on CMOS. For this research paper, a technique called Advance Leakage reduction (AL reduction) is proposed to reduce the leakage power in CMOS logic circuits. To draw our structure circuit related to CMOS like Inverter, inverted AND, and NOR etc. we have seen the power and delay for circuits. This paper incorporates, analyzing of several minimization techniques as compared with proposed work to illustrate minimization in ratio of energy and time usage and time duration for propagation. LECTOR, Source biasing, Stack ONOFIC method is observed and analyzed with the proposed method to evaluate the leakage power consumption and propagation delay for logic circuits based on CMOS. Entire work has done in LT Spice Software with 180nm library of CMOS.

Requirements of Electrical Contacts to Photovoltaic Solar Cells

1990 ◽  
Vol 184 ◽  
Author(s):  
T. A. Gessert ◽  
T. J. Coutts
Keyword(s):  
Solar Cells ◽  
Contact Resistance ◽  
Large Scale ◽  
Electrical Contacts ◽  
Specific Contact Resistance ◽  
Specific Contact ◽  
Large Scale Integration ◽  
Adverse Environmental Conditions ◽  
Scale Integration ◽  
Photovoltaic Solar Cells

ABSTRACTThe importance of contacts to photovoltaic solar cells is often underrated mainly because the required values of specific contact resistance and metal resistivity are often thought to be relatively modest compared with those associated with very large scale integration (VLSI) applications. However, due to the adverse environmental conditions experienced by solar cells, and since many of the more efficient cells are economically advantageous only when operated under solar concentration, the requirements for solar cell contacts are sometimes more severe. For example, at one-sun operation, the upper limit in specific contact resistance is usually taken to be 10−2 Ω-cm2. However, at several hundred suns, this value should be reduced to less than 10−4 Ω-cm2. Additionally, since grid line fabrication often relies on economical plating processes, porosity and contamination issues can be expected to cause reliability and stability problems once the device is fabricated. It is shown that, in practice, these metal resistivity issues can be much more important than issues relating to specific contact resistance and that the problem is similar to that of providing stable, low resistance interconnects in VLSI. This paper is concerned with the design and fabrication of collector grids on the front of the solar cells and, although the discussion is fairly general, it will center on the particular material indium phosphide. This III-V material is currently of great importance for space application because of its resistance to the damaging radiation experienced in space.

Multi-Layer Ceramic Packaging for High Frequency Mixed-Signal VLSI ASICS

2009 ◽  
Vol 6 (1) ◽  
pp. 38-41
Author(s):  
Lewis Dove
Keyword(s):  
Integrated Circuits ◽  
High Frequency ◽  
High Speed ◽  
Large Scale ◽  
Flip Chip ◽  
Data Converters ◽  
Mixed Signal ◽  
Large Scale Integration ◽  
Circuit Techniques ◽  
Scale Integration

Mixed-signal Application Specific Integrated Circuits (ASICs) have traditionally been used in test and measurement applications for a variety of functions such as data converters, pin electronics circuitry, drivers, and receivers. Over the past several years, the complexity, power density, and bandwidth of these chips has increased dramatically. This has necessitated dramatic changes in the way these chips have been packaged. As the chips have become true VLSI (Very Large Scale Integration) ICs, the number of I/Os have become too large to interconnect with wire bonds. Thus, it has become necessary to utilize flip chip interconnects. Also, the bandwidth of the high-speed signal paths and clocks has increased into the multi Gbit or GHz ranges. This requires the use of packages with good high-frequency performance which are designed using microwave circuit techniques to optimize signal integrity and to minimize signal crosstalk and noise.

423 Formation and Evaluation of Micro Fluidic Integrated Circuits by Surface Micromachining for Large Scale Integration

2008 ◽  
Vol 2008.8 (0) ◽  
pp. 147-148
Author(s):  
Hidekuni TAKAO ◽  
Nobuhiro TANAKA ◽  
Masanori SUGIURA ◽  
Kazuaki SAWADA ◽  
Makoto ISHIDA
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Surface Micromachining ◽  
Large Scale Integration ◽  
Scale Integration

Crystalline Si Films for Integrated Active-Matrix Liquid-Crystal Displays

MRS Bulletin ◽  
1996 ◽  
Vol 21 (3) ◽  
pp. 39-48 ◽  
Author(s):  
James S. Im ◽  
Robert S. Sposili
Keyword(s):  
Liquid Crystal ◽  
Large Scale ◽  
Liquid Crystal Display ◽  
Liquid Crystal Displays ◽  
Vlsi Circuits ◽  
Active Matrix ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Matrix Liquid ◽  
Si Wafer

The fabrication of thin-film-transistor (TFT) devices on a transparent substrate lies at the heart of active-matrix-liquid-crystal-display (AMLCD) technology. This is both good and bad. On one hand it is a difficult task to manufacture millions of intricate semiconductor devices reliably over such large display substrates. On the positive side, AMLCD technology can aspire to become much more than a “display” technology. The idea is as follows: It is possible for one to readily fabricate additional transistors to execute various electronic functions—those that would otherwise be handled by separate large-scale-integration (LSI) and very large-scale-integration (VLSI) circuits—on the periphery of the display. Since this can be done, in principle, with no—or a minimal number of—additional processing steps, substantial cost reduction is possible and significant value can be added to the final product.Doing so and doing it well can ultimately lead to “system-on-glass” products in which the entire electronic circuitry needed for a product is incorporated directly onto a glass substrate. This means that integrated active-matrix liquid-crystal displays (IAMLCDs) have the potential to bypass conventional Si-wafer-based products and may lead TFT technology to compete directly against Si-wafer-based monolithic integrated circuits.

scholarly journals Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices

2015 ◽  
Vol 28 (1) ◽  
pp. 153-164 ◽  
Author(s):  
Dmitry Boychenko ◽  
Oleg Kalashnikov ◽  
Alexander Nikiforov ◽  
Anastasija Ulanova ◽  
Dmitry Bobrovsky ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Test Procedure ◽  
Functional Tests ◽  
Total Ionizing Dose ◽  
Radiation Test ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Total Ionizing Dose Effects ◽  
Basic Radiation

Total ionizing dose (TID) effects and radiation tests of complex multifunctional Very-large-scale integration (VLSI) integrated circuits (ICs) rise up some particularities as compared to conventional ?simple? ICs. The main difficulty is to organize informative and quick functional tests directly under irradiation. Functional tests approach specified for complex multifunctional VLSI devices is presented and the basic radiation test procedure is discussed in application to some typical examples.

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