Effects of Gamma-Ray Irradiation and Thermal Annealing on Characteristics of 3C-SIC MOS Structure

1992 ◽  
Vol 281 ◽  
Author(s):  
M. Yoshikawa ◽  
Y. Morita ◽  
H. Itoh ◽  
I. Nashiyama ◽  
H. Okumura ◽  
...  
Keyword(s):  
Thermal Annealing ◽  
Room Temperature ◽  
Gamma Ray ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Mos Structure ◽  
Capacitance Voltage ◽  
Different Types ◽  
Gamma Ray Irradiation ◽  
Mos Structures

ABSTRACTThermal annealing of interface traps introduced by 60Co gamma-ray irradiation in 3C-SiC metal-oxide-semiconductor (MOS) structures have been studied by high-frequency capacitance-voltage measurements. By isochronal annealing up to 400°C, two recovery stages were observed, which correspond to the annealing of two different types of the interface traps. It was found that introduction of the interface traps was suppressed by thermal annealing before irradiation. Radiation tolerance of 3C-SiC MOS structure is explained in terms of the room temperature annealing of the interface traps introduced by irradiation.

scholarly journals The gamma-ray irradiation sensitivity and dosimetric information instability of RADFET dosimeter

2013 ◽  
Vol 28 (4) ◽  
pp. 415-421 ◽  
Author(s):  
Milic Pejovic
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Room Temperature ◽  
Gamma Ray ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Gamma Ray Irradiation

The gamma-ray irradiation sensitivity to radiation dose range from 0.5 Gy to 5 Gy and post-irradiation annealing at room and elevated temperatures have been studied for p-channel metal-oxide-semiconductor field effect transistors (also known as radiation sensitive field effect transistors or pMOS dosimeters) with gate oxide thicknesses of 400 nm and 1 mm. The gate biases during the irradiation were 0 and 5 V and 5 V during the annealing. The radiation and the post-irradiation sensitivity were followed by measuring the threshold voltage shift, which was determined by using transfer characteristics in saturation and reader circuit characteristics. The dependence of threshold voltage shift DVT on absorbed radiation dose D and annealing time was assessed. The results show that there is a linear dependence between DVT and D during irradiation, so that the sensitivity can be defined as DVT/D for the investigated dose interval. The annealing of irradiated metal-oxide-semiconductor field effect transistors at different temperatures ranging from room temperature up to 150?C was performed to monitor the dosimetric information loss. The results indicated that the dosimeters information is saved up to 600 hours at room temperature, whereas the annealing at 150?C leads to the complete loss of dosimetric information in the same period of time. The mechanisms responsible for the threshold voltage shift during the irradiation and the later annealing have been discussed also.

Recovery of the Electrical Characteristics of SiC MOSFETs Irradiated with Gamma-Rays by Thermal Treatments

2015 ◽  
Vol 821-823 ◽  
pp. 705-708 ◽  
Author(s):  
Takashi Yokoseki ◽  
Hiroshi Abe ◽  
Takahiro Makino ◽  
Shinobu Onoda ◽  
Yuki Tanaka ◽  
...  
Keyword(s):  
Room Temperature ◽  
Vertical Structure ◽  
Gamma Ray ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Thermal Treatments ◽  
Electrical Characteristics ◽  
Gamma Ray Irradiation ◽  
Subsequent Thermal Annealing

Effects of gamma-ray irradiation and subsequent thermal annealing on the characteristics of vertical structure power Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) fabricated on 4H-SiC were studied. After irradiation at 1.2 MGy, the drain current – gate voltage curves of the MOSFETs shifted to the negative voltage side and the leakage drain current at inverse voltage increased. No significant change in the degraded electrical characteristics of SiC MOSFETs was observed by room temperature annealing. The degraded characteristics of SiC MOSFETs began to recover by annealing above 120 °C, and their characteristics reached almost the initial ones by annealing at 360 °C.

scholarly journals Effect of size and position of gold nanocrystals embedded in gate oxide of SiO2/Si MOS structures

2016 ◽  
Vol 06 (01) ◽  
pp. 1650001 ◽  
Author(s):  
Chaitali Chakraborty ◽  
Chayanika Bose
Keyword(s):  
Oxide Semiconductor ◽  
Internal Electric Field ◽  
Interface Traps ◽  
Gold Nanocrystals ◽  
Simulation Tools ◽  
Voltage Curve ◽  
Capacitance Voltage ◽  
Mos Structures ◽  
Mos Device

The influence of single and double layered gold (Au) nanocrystals (NC), embedded in SiO2 matrix, on the electrical characteristics of metal–oxide–semiconductor (MOS) structures is reported in this communication. The size and position of the NCs are varied and study is made using Sentaurus TCAD simulation tools. In a single NC-layered MOS structure, the role of NCs is more prominent when they are placed closer to SiO2/Si[Formula: see text]substrate interface than to SiO2/Al–gate interface. In MOS structures with larger NC dots and double layered NCs, the charge storage capacity is increased due to charging of the dielectric in the presence of NCs. Higher breakdown voltage and smaller leakage current are also obtained in the case of dual NC-layered MOS device. A new phenomenon of smearing out of the capacitance–voltage curve is observed in the presence of dual NC layer indicating generation of interface traps. An internal electric field developed between these two charged NC layers is expected to generate such interface traps at the SiO2/Si interface.

Generation of Interface Traps and Oxide-Trapped Charge in 6H-SiC Metal-Oxide-Semiconductor Transistors by Gamma-Ray Irradiation

1998 ◽  
Vol 37 (Part 2, No. 8B) ◽  
pp. L1002-L1004 ◽  
Author(s):  
Takeshi Ohshima ◽  
Masahito Yoshikawa ◽  
Hisayoshi Itoh ◽  
Yasushi Aoki ◽  
Isamu Nashiyama
Keyword(s):  
Metal Oxide ◽  
Gamma Ray ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Gamma Ray Irradiation ◽  
Oxide Trapped Charge ◽  
Trapped Charge

One-step synthesis of well-dispersed polypyrrole copolymers under gamma-ray irradiation

2021 ◽  
Vol 12 (5) ◽  
pp. 645-649
Author(s):  
Yu Gu ◽  
Yuqing Qiao ◽  
Yusen Meng ◽  
Ming Yu ◽  
Bowu Zhang ◽  
...  
Keyword(s):  
Room Temperature ◽  
Gamma Ray ◽  
Gamma Ray Irradiation ◽  
One Step ◽  
First Time

Herein, we report for the first time the synthesis of polypyrrole copolymers with good solvent-dispersibility under gamma-ray irradiation at room temperature in air.

Change in Characteristics of SiC MOSFETs by Gamma-Ray Irradiation at High Temperature

2016 ◽  
Vol 858 ◽  
pp. 860-863 ◽  
Author(s):  
Takuma Matsuda ◽  
Takashi Yokoseki ◽  
Satoshi Mitomo ◽  
Koichi Murata ◽  
Takahiro Makino ◽  
...  
Keyword(s):  
Field Effect ◽  
Gamma Ray ◽  
Field Effect Transistors ◽  
Absorbed Dose ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Radiation Response ◽  
Electrical Characteristics ◽  
Gamma Ray Irradiation

Radiation response of 4H-SiC vertical power Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) was investigated at 150°C up to 10.4 MGy. Until irradiation at 1.2 MGy, the drain current – gate voltage curves of the SiC MOSFETs shifted to the negative voltage side, and the leakage of drain current at gate voltages below threshold voltage increased with increasing absorbed dose. However, no significant change in the electrical characteristics of SiC MOSFETs was observed at doses above 1.2 MGy. For blocking characteristics, there were no degradations of the SiC MOSFETs irradiated at 150°C even after irradiated at 10.4 MGy.

Radiation hardness of β-Ga2O3 metal-oxide-semiconductor field-effect transistors against gamma-ray irradiation

2018 ◽  
Vol 112 (2) ◽  
pp. 023503 ◽  
Author(s):  
Man Hoi Wong ◽  
Akinori Takeyama ◽  
Takahiro Makino ◽  
Takeshi Ohshima ◽  
Kohei Sasaki ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Gamma Ray ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Radiation Hardness ◽  
Oxide Semiconductor ◽  
Gamma Ray Irradiation

On Separating Oxide Charges and Interface Charges in 4H-SiC Metal-Oxide-Semiconductor Devices

2006 ◽  
Vol 527-529 ◽  
pp. 1007-1010 ◽  
Author(s):  
Daniel B. Habersat ◽  
Aivars J. Lelis ◽  
G. Lopez ◽  
J.M. McGarrity ◽  
F. Barry McLean
Keyword(s):  
Room Temperature ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Interface Charges ◽  
Flatband Voltage ◽  
Oxide Traps ◽  
P Type

We have investigated the distribution of oxide traps and interface traps in 4H Silicon Carbide MOS devices. The density of interface traps, Dit, was characterized using standard C-V techniques on capacitors and charge pumping on MOSFETs. The number of oxide traps, NOT, was then calculated by measuring the flatband voltage VFB in p-type MOS capacitors. The amount that the measured flatband voltage shifts from ideal, minus the contributions due to the number of filled interface traps Nit, gives an estimate for the number of oxide charges present. We found Dit to be in the low 1011cm−2eV−1 range in midgap and approaching 1012 −1013cm−2eV−1 near the band edges. This corresponds to an Nit of roughly 2.5 ⋅1011cm−2 for a typical capacitor in flatband at room temperature. This data combined with measurements of VFB indicates the presence of roughly 1.3 ⋅1012cm−2 positive NOT charges in the oxide near the interface for our samples.

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